Datasheet > 9FG104YFT

9FG104YFT

更新时间： 2023-07-15 00:00:00

品牌	Logo	应用领域
艾迪悌 - IDT		光电二极管
页数	文件大小	规格书
17页	238K
描述
Processor Specific Clock Generator, 400MHz, PDSO28, 0.209 INCH, MO-150N, SSOP-28

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9FG104YFT 数据手册

ICS9FG104

Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA

SMBus Table: Reserved Register

Byte 7

Pin #

Name

Control Function

Reserved

Type

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

SMBus Table: Reserved Register

Byte 8

Pin #

Name

Control Function

Type

PWD

Reserved

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SMBus Table: M/N Programming Enable

Byte 9

Pin #

Name

Control Function

M/N Prog. Enable

Reserved

REFOUT Enable

Reserved

Type

PWD

M/N_Enable

Disable

Enable

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

REFOUT_En

Disable

Enable

Reserved

SMBus Table: PLL Frequency Control Register

Byte 10

Pin #

Name

Control Function

Type

PWD

PLL N Div8

PLL N Div9

PLL M Div5

PLL M Div4

PLL M Div3

PLL M Div2

PLL M Div1

PLL M Div0

N Divider Prog bit 8

N Divider Prog bit 9

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

The decimal representation of M

and N Divider in Byte 11 and 12 will

configure the PLL VCO frequency.

Default at power up = latch-in or

Byte 0 Rom table. VCO Frequency

= 14.318 x [NDiv(9:0)+8] /

M Divider Programming

bit (5:0)

[MDiv(5:0)+2]

IDT^TM/ICS^TMFrequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA

0839O—12/03/08

1...4 5 678 9 10...17

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