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9DB423BGLF PDF预览

9DB423BGLF

更新时间: 2024-01-22 21:30:01
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器逻辑集成电路光电二极管PC
页数 文件大小 规格书
19页 282K
描述
Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI

9DB423BGLF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP-28针数:28
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.82
系列:9DB输入调节:DIFFERENTIAL MUX
JESD-30 代码:R-PDSO-G28JESD-609代码:e3
长度:9.7 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:28
实输出次数:4最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP28,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.05 ns座面最大高度:1.2 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
Base Number Matches:1

9DB423BGLF 数据手册

 浏览型号9DB423BGLF的Datasheet PDF文件第3页浏览型号9DB423BGLF的Datasheet PDF文件第4页浏览型号9DB423BGLF的Datasheet PDF文件第5页浏览型号9DB423BGLF的Datasheet PDF文件第7页浏览型号9DB423BGLF的Datasheet PDF文件第8页浏览型号9DB423BGLF的Datasheet PDF文件第9页 
9DB423B  
Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI  
Electrical Characteristics - Clock Input Parameters  
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
600  
TYP  
800  
MAX  
1150  
UNITS NOTES  
Differential inputs  
(single-ended measurement)  
Differential inputs  
Input High Voltage - DIF_IN  
VIHDIF  
mV  
mV  
mV  
1
1
1
Input Low Voltage - DIF_IN  
VILDIF  
VCOM  
V
SS - 300  
300  
0
300  
(single-ended measurement)  
Input Common Mode Voltage -  
DIF_IN  
Common Mode Input Voltage  
1000  
Input Amplitude - DIF_IN  
Input Slew Rate - DIF_IN  
Input Leakage Current  
VSWING  
dv/dt  
IIN  
Peak to Peak value  
Measured differentially  
VIN = VDD , VIN = GND  
300  
0.4  
-5  
1450  
8
5
mV  
V/ns  
uA  
1
1,2  
1
Input Duty Cycle  
dtin  
Measurement from differential wavefrom  
Differential Measurement  
45  
0
55  
125  
%
1
Input Jitter - Cycle to Cycle  
JDIFIn  
ps  
1
1 Guaranteed by design and characterization, not 100% tested in production.  
2Slew rate measured through Vswing min centered around differential zero  
IDT® Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI  
1437B - 02/04/10  
6

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