Datasheet > 9DB401GLFT

9DB401GLFT

更新时间： 2024-02-01 23:49:36

品牌	Logo	应用领域
艾迪悌 - IDT		光电二极管
页数	文件大小	规格书
16页	168K
描述
Clock Driver, PDSO28

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技术参数
数据手册

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9DB401GLFT 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	TSSOP, TSSOP28,.25	Reach Compliance Code：	compliant
风险等级：	5.84	JESD-30 代码：	R-PDSO-G28
JESD-609代码：	e3	湿度敏感等级：	1
端子数量：	28	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装等效代码：	TSSOP28,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源：	3.3 V	认证状态：	Not Qualified
子类别：	Clock Drivers	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	温度等级：	COMMERCIAL
端子面层：	Matte Tin (Sn) - annealed	端子形式：	GULL WING
端子节距：	0.635 mm	端子位置：	DUAL
Base Number Matches：	1

9DB401GLFT 数据手册

Integrated

Circuit

ICS9DB401

Systems, Inc.

Pin Decription When OE_INV = 0

PIN #

PIN NAME

VDD

SRC_IN

SRC_IN#

GND

VDD

DIF_1

DIF_1#

PIN TYPE

DESCRIPTION

PWR

OUT

Power supply, nominal 3.3V

0.7 V Differential SRC TRUE input

0.7 V Differential SRC COMPLEMENTARY input

Ground pin.

Power supply, nominal 3.3V

0.7V differential true clock output

0.7V differential complement clock output

Active high input for enabling output 1.

0 = tri-state outputs, 1= enable outputs

0.7V differential true clock output

0.7V differential complement clock output

Power supply, nominal 3.3V

OE_1

DIF_2

DIF_2#

VDD

OUT

PWR

Input to select Bypass(fan-out) or PLL (ZDB) mode

0 = Bypass mode, 1= PLL mode

Clock pin of SMBus circuitry, 5V tolerant.

Data pin for SMBus circuitry, 5V tolerant.

BYPASS#/PLL

SCLK

SDATA

I/O

Asynchronous active low input pin used to power down the device. The

internal clocks are disabled and the VCO and the crystal are stopped.

PD#

SRC_STOP#

HIGH_BW#

Active low input to stop SRC outputs.

3.3V input for selecting PLL Band Width

0 = High, 1= Low

VDD

DIF_5#

DIF_5

PWR

OUT

Power supply, nominal 3.3V

0.7V differential complement clock output

0.7V differential true clock output

Active high input for enabling output 6.

0 = tri-state outputs, 1= enable outputs

0.7V differential complement clock output

0.7V differential true clock output

OE_6

DIF_6#

DIF_6

VDD

OUT

PWR

Power supply, nominal 3.3V

This latched input selects the polarity of the OE pins.

0 = OE pins active high, 1 = OE pins active low (OE#)

This pin establishes the reference current for the differential current-

mode output pairs. This pin requires a fixed precision resistor tied to

ground in order to establish the appropriate current. 475 ohms is the

standard value.

OE_INV

IREF

OUT

GNDA

VDDA

PWR

Ground pin for the PLL core.

3.3V power for the PLL core.

1014A—08/15/05

123 4 5 6 7...16

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