9DB108YFT PDF预览

9DB108YFT

更新时间: 2025-09-12 19:58:39
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
16页 144K
描述
PLL Based Clock Driver, 9DB Series, 8 True Output(s), 0 Inverted Output(s), PDSO48, MO-118, SSOP-48

9DB108YFT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP,针数:48
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.58系列:9DB
输入调节:DIFFERENTIALJESD-30 代码:R-PDSO-G48
JESD-609代码:e0长度:15.875 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER功能数量:1
反相输出次数:端子数量:48
实输出次数:8最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):225认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.05 ns座面最大高度:2.8 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:7.5 mm最小 fmax:220 MHz
Base Number Matches:1

9DB108YFT 数据手册

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Integrated  
Circuit  
Systems, Inc.  
ICS9DB108  
(Not recommended for new designs)  
Eight Output Differential Buffer for PCI-Express  
Recommended Application:  
Pin Configuration  
DB800 Intel Yellow Cover part with PCI-Express support.  
SRC_DIV#  
VDD  
1
2
48 VDDA  
47 GNDA  
Output Features:  
GND  
3
4
5
6
46  
IREF  
8 - 0.7V current-mode differential output pairs  
Supports zero delay buffer mode and fanout mode  
Bandwidth programming available  
SRC_IN  
SRC_IN#  
OE_0  
45 LOCK  
44 OE_7  
43 OE_4  
7
8
9
10  
11  
12  
13  
42  
41  
40  
39 VDD  
38  
37  
36 OE_6  
35 OE_5  
34  
33  
32 GND  
31 VDD  
30  
29  
OE_3  
DIF_7  
DIF_7#  
GND  
Key Specifications:  
DIF_0  
DIF_0#  
GND  
VDD  
DIF_1  
DIF_1#  
Outputs cycle-cycle jitter < 50ps  
Outputs skew: 50ps  
+/- 300ppm frequency accuracy on output clocks  
DIF_6  
DIF_6#  
Features/Benefits:  
Supports tight ppm accuracy clocks for Serial-ATA  
Spread spectrum modulation tolerant, 0 to -0.5% down  
spread and +/- 0.25% center spread  
OE_1 14  
OE_2 15  
DIF_5  
DIF_5#  
16  
17  
18  
19  
20  
21  
22  
23  
24  
DIF_2  
DIF_2#  
GND  
VDD  
DIF_3  
DIF_3#  
Supports undriven differential output pair in PD# and  
SRC_STOP# for power management.  
DIF_4  
DIF_4#  
28 HIGH_BW#  
27 SRC_STOP#  
26 PD#  
BYPASS#/PLL  
SCLK  
25 GND  
SDATA  
48-pin SSOP & TSSOP  
0723G—12/02/08  

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