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97U877AKLF-T PDF预览

97U877AKLF-T

更新时间: 2024-02-18 07:32:23
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
13页 1125K
描述
PLL Based Clock Driver, 97U Series, 10 True Output(s), 0 Inverted Output(s), MLF-40

97U877AKLF-T 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:DFN
包装说明:MLF-40针数:40
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.17系列:97U
输入调节:DIFFERENTIALJESD-30 代码:S-XQCC-N40
JESD-609代码:e3长度:6 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER最大I(ol):0.009 A
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:40
实输出次数:10最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC40,.24SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:1.8 V认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.04 ns座面最大高度:0.9 mm
子类别:Clock Drivers最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:6 mm
最小 fmax:350 MHzBase Number Matches:1

97U877AKLF-T 数据手册

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ICS97U877AHLF/AKLF  
Advance Information  
Recommended Operating Condition  
(see note1)  
TA = 0 - 70°C; Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)  
PARAMETER  
Supply Voltage  
SYMBOL  
CONDITIONS  
MIN  
1.7  
TYP  
1.8  
MAX  
1.9  
UNITS  
V
VDDQ, AVDD  
CLK_INT, CLK_INC, FB_INC,  
FB_INT  
OE, OS  
CLK_INT, CLK_INC, FB_INC,  
FB_INT  
OE, OS  
0.35 x VDDQ  
0.35 x VDDQ  
V
V
V
V
V
Low level input voltage  
High level input voltage  
VIL  
0.65 x VDDQ  
0.65 x VDDQ  
-0.3  
VIH  
VIN  
DC input signal voltage  
(note 2)  
VDDQ + 0.3  
VDDQ + 0.4  
DC - CLK_INT, CLK_INC,  
FB_INC, FB_INT  
AC - CLK_INT, CLK_INC,  
FB_INC, FB_INT  
0.3  
0.6  
V
V
V
V
Differential input signal  
voltage (note 3)  
VID  
VDDQ + 0.4  
Output differential cross-  
voltage (note 4)  
Input differential cross-  
voltage (note 4)  
VOX  
VIX  
VDDQ/2 - 0.10  
VDDQ/2 + 0.10  
VDDQ/2 - 0.15 VDD/2 VDDQ2 + 0.15  
High level output current  
IOH  
IOL  
-9  
9
mA  
mA  
Low level output current  
Operating free-air  
temperature  
TA  
0
70  
°C  
Notes:  
1. Unused inputs must be held high or low to prevent them from floating.  
2. DC input signal voltage specifies the allowable DC execution of differential input.  
3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP]  
required for switching, where VTR is the true input level and VCP is the  
complementary input level.  
4. Differential cross-point voltage is expected to track variations of VDDQ and is the  
voltage at which the differential signal must be crossing.  
0792—12/18/03  
5

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