Datasheet > 97U877AKLF-T

97U877AKLF-T

更新时间： 2024-02-08 20:49:15

品牌	Logo	应用领域
艾迪悌 - IDT		驱动逻辑集成电路
页数	文件大小	规格书
13页	1125K
描述
PLL Based Clock Driver, 97U Series, 10 True Output(s), 0 Inverted Output(s), MLF-40

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技术参数
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97U877AKLF-T 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	DFN
包装说明：	MLF-40	针数：	40
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.17	系列：	97U
输入调节：	DIFFERENTIAL	JESD-30 代码：	S-XQCC-N40
JESD-609代码：	e3	长度：	6 mm
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	最大I（ol）：	0.009 A
湿度敏感等级：	3	功能数量：	1
反相输出次数：		端子数量：	40
实输出次数：	10	最高工作温度：	70 °C
最低工作温度：		输出特性：	3-STATE
封装主体材料：	UNSPECIFIED	封装代码：	HVQCCN
封装等效代码：	LCC40,.24SQ,20	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	峰值回流温度（摄氏度）：	260
电源：	1.8 V	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.04 ns	座面最大高度：	0.9 mm
子类别：	Clock Drivers	最大供电电压 (Vsup)：	1.9 V
最小供电电压 (Vsup)：	1.7 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	温度等级：	COMMERCIAL
端子面层：	Matte Tin (Sn) - annealed	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	6 mm
最小 fmax：	350 MHz	Base Number Matches：	1

97U877AKLF-T 数据手册

ICS97U877AHLF/AKLF

Advance Information

Pin Descriptions

Terminal

Name

Electrical

Characteristics

Description

AGND

Analog Ground

Analog power

Ground

AV_DD

1.8 V nominal

CLK_INT

CLK_INC

FB_INT

Clock input with a (10K-100K Ohm) pulldown resistor

Complentary clock input with a (10K-100K Ohm) pulldown resistor

Feedback clock input

Differential input

FB_INC

FB_OUTT

FB_OUTC

Complementary feedback clock input

Feedback clock output

Differential input

Differential output

LVCMOS input

Ground

Complementary feedback clock output

Output Enable (Asynchronous)

Output Select (tied to GND or V_DDQ

Ground

)

GND

V_DDQ

Logic and output power

Clock outputs

1.8V nominal

CLKT[0:9]

CLKC[0:9]

Differential outputs

Complementary clock outputs

No ball

The PLL clock buffer, ICS97U877, is designed for aV_DDQof 1.8V, a AV_DDof 1.8V and differential data input and output

levels. Package options include a plastic 52-ball VFBGA and a 40-pin MLF.

ICS97U877 is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to ten differential

pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock outputs (FB_OUTT, FBOUTC).

The clock outputs are controlled by the input clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT, FB_INC), the

LVCMOS program pins (OE, OS) and the Analog Power input (AVDD).When OE is low, the outputs (except FB_OUTT/

FB_OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency.OS (Output Select) is a

program pin that must be tied to GND orV_DDQ.When OS is high, OE will function as described above.When OS is low,

OEhasnoeffectonCLKT7/CLKC7(theyarefreerunninginadditiontoFB_OUTT/FB_OUTC).WhenAV_DDisgrounded,

the PLL is turned off and bypassed for test purposes.

When both clock signals (CLK_INT, CLK_INC) are logic low, the device will enter a low power mode. An input logic

detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform

alowpowerstatewherealloutputs, thefeedbackandthePLLareOFF.Whentheinputstransitionfrombothbeinglogic

low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL

willobtainphaselockbetweenthefeedbackclockpair(FB_INT, FB_INC)andtheinputclockpair(CLK_INT, CLK_INC)

within the specified stabilization time t_STAB

The PLL in ICS97U877 clock driver uses the input clocks (CLK_INT, CLK_INC) and the feedback clocks (FB_INT,

FB_INC)toprovidehigh-performance, low-skew, low-jitteroutputdifferentialclocks(CLKT[0:9], CLKC[0:9]).ICS97U877

is also able to track Spread Spectrum Clocking (SSC) for reduced EMI.

ICS97U877 is characterized for operation from 0°C to 70°C.

0792—12/18/03

123 4 5 6 7...13

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与97U877AKLF-T相关器件

型号	品牌	描述	获取价格	数据表
97U877AKT	IDT	VFQFPN-40, Reel	获取价格
97U877HLF-T	IDT	Clock Driver	获取价格
97U877KLF-T	IDT	Clock Driver	获取价格
97U877K-T	IDT	Clock Driver	获取价格
97U877YHLF-T	IDT	PLL Based Clock Driver, 97U Series, 10 True Output(s), 0 Inverted Output(s), PBGA52, LEAD	获取价格
97U877YKLF-T	IDT	PLL Based Clock Driver, 97U Series, 10 True Output(s), 0 Inverted Output(s), PQCC40, LEAD	获取价格

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