5秒后页面跳转
97U877AKLF-T PDF预览

97U877AKLF-T

更新时间: 2024-02-20 23:17:25
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
13页 1125K
描述
PLL Based Clock Driver, 97U Series, 10 True Output(s), 0 Inverted Output(s), MLF-40

97U877AKLF-T 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:DFN
包装说明:MLF-40针数:40
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.17系列:97U
输入调节:DIFFERENTIALJESD-30 代码:S-XQCC-N40
JESD-609代码:e3长度:6 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER最大I(ol):0.009 A
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:40
实输出次数:10最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC40,.24SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:1.8 V认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.04 ns座面最大高度:0.9 mm
子类别:Clock Drivers最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:6 mm
最小 fmax:350 MHzBase Number Matches:1

97U877AKLF-T 数据手册

 浏览型号97U877AKLF-T的Datasheet PDF文件第2页浏览型号97U877AKLF-T的Datasheet PDF文件第3页浏览型号97U877AKLF-T的Datasheet PDF文件第4页浏览型号97U877AKLF-T的Datasheet PDF文件第5页浏览型号97U877AKLF-T的Datasheet PDF文件第6页浏览型号97U877AKLF-T的Datasheet PDF文件第7页 
ICS97U877AHLF/AKLF  
Integrated  
Circuit  
Systems,Inc.  
Advance Information  
1.8V Wide Range Frequency Clock Driver  
RecommendedApplication:  
Pin Configuration  
DDR2 Memory Modules / Zero Delay Board Fan Out  
Provides complete DDR DIMM logic solution with  
ICSSSTU32864  
1
2
3
4
5
6
A
B
C
D
E
F
ProductDescription/Features:  
Low skew, low jitter PLL clock driver  
1 to 10 differential clock distribution (SSTL_18)  
Feedback pins for input to output synchronization  
Spread Spectrum tolerant inputs  
G
H
J
Auto PD when input signal is at a certain logic state  
K
SwitchingCharacteristics:  
97U877AHLF 52-Ball BGA  
Period jitter:40ps  
Half-period jitter: 60ps  
CYCLE - CYCLE jitter 40ps  
OUTPUT - OUTPUT skew: 40ps  
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
CLKT1  
CLKC1  
CLKC2  
CLKT2  
CLK_INT  
CLK_INC  
AGND  
AVDD  
CLKT3  
CLKC3  
CLKT0  
GND  
GND  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
GND  
CLKC0  
GND  
NB  
VDDQ  
NB  
NB  
VDDQ  
NB  
CLKC5  
GND  
NB  
VDDQ  
NB  
NB  
VDDQ  
NB  
CLKT5  
GND  
GND  
OS  
VDDQ  
OE  
VDDQ  
GND  
GND  
CLKC9  
CLKT6  
CLKC6  
CLKC7  
CLKT7  
FB_INT  
FB_INC  
FB_OUTC  
FB_OUTT  
CLKT8  
GND  
CLKC4  
GND  
CLKT4  
GND  
CLKT9  
K
CLKC8  
Block Diagram  
CLKT0  
CLKC0  
LD* or OE  
OE  
40  
31  
Powerdown  
Control and  
Test Logic  
CLKT1  
CLKC1  
LD*, OS or OE  
OS  
AVDD  
30  
1
VDDQ  
CLKC7  
CLKT7  
VDDQ  
FB_INT  
FB_INC  
FB_OUTC  
FB_OUTT  
VDDQ  
OE  
CLKT2  
CLKC2  
CLKC2  
CLKT2  
CLK_INT  
CLK_INC  
VDDQ  
PLL bypass  
LD*  
CLKT3  
CLKC3  
CLKT4  
CLKC4  
ICS97U877AKLF  
AGND  
AVDD  
VDDQ  
CLKT5  
CLKC5  
CLK_INT  
CLKT6  
CLKC6  
GND 10  
21  
OS  
CLK_INC  
10K-100k  
11  
20  
CLKT7  
CLKC7  
PLL  
GND  
CLKT8  
CLKC8  
FB_INT  
FB_INC  
CLKT9  
CLKC9  
* The Logic Detect (LD) powers down the device when a  
logic low is applied to both CLK_INT and CLK_INC.  
40-Pin MLF  
FB_OUTT  
FB_OUTC  
0792—12/18/03  
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.  
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.  

与97U877AKLF-T相关器件

型号 品牌 描述 获取价格 数据表
97U877AKT IDT VFQFPN-40, Reel

获取价格

97U877HLF-T IDT Clock Driver

获取价格

97U877KLF-T IDT Clock Driver

获取价格

97U877K-T IDT Clock Driver

获取价格

97U877YHLF-T IDT PLL Based Clock Driver, 97U Series, 10 True Output(s), 0 Inverted Output(s), PBGA52, LEAD

获取价格

97U877YKLF-T IDT PLL Based Clock Driver, 97U Series, 10 True Output(s), 0 Inverted Output(s), PQCC40, LEAD

获取价格