97SD3248BRPQI

更新时间： 2024-01-25 13:12:32

阅读下载

中文翻译

获取价格

如果您发现信息不准确，欢迎纠错

97SD3248BRPQI 数据手册

97SD3248

1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM

DQM Control

The DQM mask the bytes of the DQ data. The timing of DQM is different during reading and writing.

Reading: When data is read, the output buffer can be controlled by DQM. By setting DQM to Low, the output

buffer becomes Low-Z, enabling data output. By setting DQM to High, the output buffer becomes High-Z and

the corresponding data is not output. However, internal reading operations continue. The latency of DQM

during reading is 2 clocks.

Writing: Input data can be masked by DQM. By setting DQM to Low, data can be written. In addition, when

DQM is set to High, the corresponding data is not written, and previous data is held. The latency of DQM

during writing is 0 clock.

Reading

02.04.05 Rev 3

All data sheets are subject to change without notice 35

中文翻译

下载PDF

型号	品牌	获取价格	描述	数据表
97SD3248BRPQK	MAXWELL	获取价格	Synchronous DRAM, 32MX48, 6ns, CMOS, PQFP132, QFP-132
97SD3248RPME	MAXWELL	获取价格	Synchronous DRAM, 32MX48, 6ns, CMOS, STACK, QFP-132
97SD3248RPMI	MAXWELL	获取价格	Synchronous DRAM, 32MX48, 6ns, CMOS, STACK, QFP-132
97SD3248RPQE	MAXWELL	获取价格	1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks
97SD3248RPQH	MAXWELL	获取价格	1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks
97SD3248RPQI	MAXWELL	获取价格	1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks
97SD3248RPQK	MAXWELL	获取价格	1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks
97SMOK-18-33V	WK	获取价格	Crystal Clock Oscillators
97SMOK-5V	WK	获取价格	Crystal Clock Oscillators
97SMOKE	WK	获取价格	Crystal Clock Oscillators