97SD3248BRPQI

更新时间： 2024-01-16 01:13:32

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97SD3248BRPQI 数据手册

97SD3248

1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM

Clock suspend mode: By driving CKE to Low during a bank-active or read/write operation, the SDRAM

enters clock suspend mode. During clock suspend mode, external input signals are ignored and the internal

state is maintained. When CKE is driven High, the SDRAM terminates clock suspend mode, and command

input is enabled from the next clock. For more details, refer to the “CKE Truth Table”.

Power-up sequence: The SDRAM should use the following sequence during power-up:

The CLK, CKE, CS, DQM and DQ pins stay low until power stabilizes.

The CLK pin is stable within 100ms after power stabilizes before the following initialization sequence.

The CKE and DQM is driven high between when power stabilizes and the initialization sequence.

This SDRAM has V clamp diodes for CLK, CKE, CS, DQM and DQ pins. If these pins go high before

power up, the large^Cc^Current flows from these pins to V through the diodes.

Initialization sequence: When 200ms or more has past after the power up sequence, all banks must be

precharged using the precharge command (PALL). After t_RPdelay, set 8 or more auto refresh commands

(REF). Set the mode register set command (MRS) to initialize the mode register. It is recommended that by

keeping DQM and CKE High, the output buffer becomes High-Z during initialization sequence, to avoid DQ

bus contention on a memory system formed with a number of devices.

02.04.05 Rev 3

All data sheets are subject to change without notice 37

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型号	品牌	描述	获取价格	数据表
97SD3248BRPQK	MAXWELL	Synchronous DRAM, 32MX48, 6ns, CMOS, PQFP132, QFP-132	获取价格
97SD3248RPME	MAXWELL	Synchronous DRAM, 32MX48, 6ns, CMOS, STACK, QFP-132	获取价格
97SD3248RPMI	MAXWELL	Synchronous DRAM, 32MX48, 6ns, CMOS, STACK, QFP-132	获取价格
97SD3248RPQE	MAXWELL	1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks	获取价格
97SD3248RPQH	MAXWELL	1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks	获取价格
97SD3248RPQI	MAXWELL	1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks	获取价格