Datasheet > 存储 > DRAM> 97SD3240RPMK

97SD3240RPMK

更新时间： 2024-02-11 12:56:59

品牌	Logo	应用领域
麦斯威 - MAXWELL		动态存储器
页数	文件大小	规格书
39页	741K
描述
Synchronous DRAM, 32MX40, 6ns, CMOS, STACK, QFP-132

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技术参数
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97SD3240RPMK 技术参数

生命周期：	Obsolete	包装说明：	GQFF, QFL132,1.35SQ,25
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.36	风险等级：	5.7
Is Samacsys：	N	访问模式：	FOUR BANK PAGE BURST
最长访问时间：	6 ns	其他特性：	AUTO/SELF REFRESH
最大时钟频率 (fCLK)：	133.33 MHz	I/O 类型：	COMMON
交错的突发长度：	1,2,4,8	JESD-30 代码：	S-XQFP-F132
长度：	34.29 mm	内存密度：	1342177280 bit
内存集成电路类型：	SYNCHRONOUS DRAM	内存宽度：	40
功能数量：	1	端口数量：	1
端子数量：	132	字数：	33554432 words
字数代码：	32000000	工作模式：	SYNCHRONOUS
最高工作温度：	125 °C	最低工作温度：	-55 °C
组织：	32MX40	封装主体材料：	UNSPECIFIED
封装代码：	GQFF	封装等效代码：	QFL132,1.35SQ,25
封装形状：	SQUARE	封装形式：	FLATPACK, GUARD RING
认证状态：	Not Qualified	刷新周期：	8192
反向引出线：	NO	自我刷新：	YES
连续突发长度：	1,2,4,8	最大待机电流：	0.15 A
最小待机电流：	3 V	最大压摆率：	0.575 mA
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	MILITARY
端子形式：	FLAT	端子节距：	0.635 mm
端子位置：	QUAD	总剂量：	100k Rad(Si) V
宽度：	34.29 mm	Base Number Matches：	1

97SD3240RPMK 数据手册

97SD3240

1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM

Pin Functions:

CLK (INPUT PIN): CLK is the master clock input to this pin. The other input signals are referred at CLK rising

edge.

CS 1-5 (INPUT PINS): When CS 1-5 are low, the command input cycle becomes valid. When CS 1-5 are High,

all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held.

RAS, CAS AND WE (INPUT PINS): Although these pin names are the same as those of conventional DRAMs,

they function in a different way. These pins define operation commands (read, write, etc.) depending on the

combination of their voltage levels.

A0 ^TOA12 (INPUT PINS): Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active

command cycle CLK rising edge. Column address (AY0 to AY9) is determined by A0 to A9 level at the read

or write command cycle CLK rising edge. And this column address becomes burst access start address.

A10 defines the precharge mode. When A10 = High at the precharge command cycle, all banks are pre-

charged. But when A10 = Low at the precharge command cycle, only the bank that is selected by BA0/BA1

(BS) is pre charged.

BA0/BA1 (^{INPUT PINS}): BA0/BA1 are bank select signals (BS). The memory array of the 97SD3240 is divided

into bank 0, bank 1, bank 2 and bank 3. The 97SD3240 contains 8192-row X 1024-column X 40-bit. If BA0

and BA1 is Low, bank 0 is selected. If BA0 is Low and BA1 is High, bank 1 is selected. If BA0 is High and

BA1 is Low, bank 2 is selected. If BAO is High and BA1 is High, bank 3 is selected.

CKE 1-5 (^{INPUT PIN}): This pin determines whether or not the next CLK is valid. If CKE 1-5 is High, the next

CLK rising edge is valid. If CKE 1-5 is Low, the next CLK rising edge is invalid. This pin is used for power-

down mode, clock suspend mode and self refresh mode¹.

DQM 1-5 (INPUT PINS): DQM 1-5 control input/output buffers

Read operation: If DQM 1-5 are High, the output buffer becomes High-Z. If the DQM 1-5 are Low, the output

buffer becomes Low-Z. ( The latency of DQM 1-5 during reading is 2 clock cycles.)

Write operation: If DQM 1-5 are High, the previous data is held ( the new data is not written). If the DQM 1-5

areLow, the data is written. ( The latency of DQM 1-5 during writing is 0 clock cycles.)

DQ0 TO DQ39 (DQ PINS): Data is input to and output from these pins ( DQ0 to DQ39).

AND V Q (POWER SUPPLY PINS): 3.3V is applied. ( V is for the internal circuit and V Q is for the output

CC CC CC

buffer.)

AND V Q (POWER SUPPLY PINS): Ground is connected. (V is for the internal circuit and V Q is for the

output buffer.)

1. Self refresh mode should only be used at temperatures below 70°C.

02.04.05 Rev 3

All data sheets are subject to change without notice

1...4 5 678 9 10...39

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与97SD3240RPMK相关器件

型号	品牌	描述	获取价格	数据表
97SD3240RPQE	MAXWELL	1.25Gb SDRAM 8-Meg X 40-Bit X 4-Banks	获取价格
97SD3240RPQH	MAXWELL	1.25Gb SDRAM 8-Meg X 40-Bit X 4-Banks	获取价格
97SD3240RPQI	MAXWELL	1.25Gb SDRAM 8-Meg X 40-Bit X 4-Banks	获取价格
97SD3240RPQK	MAXWELL	1.25Gb SDRAM 8-Meg X 40-Bit X 4-Banks	获取价格
97SD3248	MAXWELL	1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks	获取价格
97SD3248_06	MAXWELL	1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks	获取价格

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