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954204AGLFT PDF预览

954204AGLFT

更新时间: 2024-11-01 17:40:11
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
20页 261K
描述
Processor Specific Clock Generator, 400MHz, PDSO56, 6.10 MM, 0.50 MM PITCH, GREEN, MO-153, TSSOP-56

954204AGLFT 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:6.10 MM, 0.50 MM PITCH, GREEN, MO-153, TSSOP-56
针数:56Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.32JESD-30 代码:R-PDSO-G56
JESD-609代码:e3长度:14 mm
湿度敏感等级:1端子数量:56
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:400 MHz封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
主时钟/晶体标称频率:14.31818 MHz认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:6.1 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches:1

954204AGLFT 数据手册

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Integrated  
Circuit  
ICS954204  
Systems, Inc.  
Programmable Timing Control Hub™ for Mobile P4™ Systems  
Recommended Application:  
CK410M Compliant Main Clock with Integrated LCD Spread  
Spectrum Clock.  
PCI outputs cycle-cycle jitter < 500ps  
+/- 300ppm frequency accuracy on CPU & SRC clocks  
+/- 100ppm frequency accuracy on USB clocks  
Features/Benefits:  
Output Features:  
Supports tight ppm accuracy clocks for Serial-ATA and  
SRC  
2 - 0.7V current-mode differential CPU pairs  
5 - 0.7V current-mode differential SRC pair for SATA and  
PCI-E  
Supports programmable spread percentage and  
frequency  
1 - 0.7V current-mode differential CPU/SRC selectable  
pair  
Uses external 14.318MHz crystal, external crystal load  
caps are required for frequency tuning  
4 - PCI (33MHz)  
2 - PCICLK_F, (33MHz) free-running  
1 - USB, 48MHz  
1 - DOT, 96MHz, 0.7V current differential pair  
1 - REF, 14.318MHz  
1 - 0.7V current-mode differential LCD/SRC selectable  
pair.  
Supports undriven differential CPU, SRC pair in PD#  
for power management.  
CLKREQ pins to support SRC power management.  
Key Specifications:  
CPU outputs cycle-cycle jitter < 85ps  
SRC outputs cycle-cycle jitter < 125ps  
Pin Configuration  
Functionality  
CPU  
MHz  
SRC  
MHz  
PCI  
MHz  
REF  
MHz  
USB  
MHz  
DOT  
MHz  
VDDPCI 1  
56 PCICLK2  
FS_C FS_B FS_A  
GND 2  
PCICLK3 3  
PCICLK4 4  
PCICLK5 5  
GND 6  
55 PCI/SRC_STOP#  
54 CPU_STOP#  
53 FSLC/TEST_SEL  
52 REFOUT  
51 GND  
50 X1  
49 X2  
48 VDDREF  
47 SDATA  
46 SCLK  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
266.67 100.00 33.33  
133.33 100.00 33.33  
200.00 100.00 33.33  
166.67 100.00 33.33  
333.33 100.00 33.33  
100.00 100.00 33.33  
400.00 100.00 33.33  
200.00 100.00 33.33  
14.318  
14.318  
14.318  
14.318  
14.318  
14.318  
14.318  
14.318  
48.00  
48.00  
48.00  
48.00  
48.00  
48.00  
48.00  
48.00  
96.00  
96.00  
96.00  
96.00  
96.00  
96.00  
96.00  
96.00  
VDDPCI 7  
ITP_EN/PCICLK_F0 8  
*SELSRC_LCDCLK#/PCICLK_F1 9  
Vtt_PwrGd#/PD 10  
VDD48 11  
FSLA/USB_48MHz 12  
45 GND  
FS_C is a three-level input. Please see VIL_FS and VIH_FS specifications in the  
Input/Supply/Common Output Parameters Table for correct values. Also refer  
to the Test Clarification Table.  
1.  
2.  
GND 13  
DOTT_96MHz 14  
DOTC_96MHz 15  
44 CPUCLKT0  
43 CPUCLKC0  
42 VDDCPU  
41 CPUCLKT1  
40 CPUCLKC1  
39 IREF  
FSLB/TEST_MODE 16  
FS_B and FS_A are low-threshold inputs. Please see the VIL_FS and VIH_FS  
specifications in the Input/Supply/Common Output Parameters Table for  
correct values.  
LCDCLK_SST/SRCCLKT0 17  
LCDCLK_SSC/SRCCLKC0 18  
SRCCLKT1 19  
38 GNDA  
SRCCLKC1 20  
37 VDDA  
VDDSRC 21  
SRCCLKT2 22  
SRCCLKC2 23  
36 CPUCLKT2_ITP/SRCCLKT7  
35 CPUCLKC2_ITP/SRCCLKC7  
34 VDDSRC  
SRCCLKT3 24  
33 CLKREQA#*  
SRCCLKC3 25  
32 CLKREQB#*  
SRCCLKT4_SATA 26  
SRCCLKC4_SATA 27  
VDDSRC 28  
31 SRCCLKT5  
30 SRCCLKC5  
29 GND  
56-pin TSSOP  
*100Kohm Pull-Up Resistor  
0933D—03/16/05  

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