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950211F-T PDF预览

950211F-T

更新时间： 2024-11-06 03:12:23
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管
页数 文件大小 规格书
20页 150K
描述
Clock Generator, PDSO56

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中文翻译

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950211F-T 数据手册

 浏览型号950211F-T的Datasheet PDF文件第2页浏览型号950211F-T的Datasheet PDF文件第3页浏览型号950211F-T的Datasheet PDF文件第4页浏览型号950211F-T的Datasheet PDF文件第5页浏览型号950211F-T的Datasheet PDF文件第6页浏览型号950211F-T的Datasheet PDF文件第7页 
Integrated  
Circuit  
ICS950211  
Systems, Inc.  
Programmable Timing Control Hub™ for P4™  
Pin Configuration  
Recommended Application:  
VDDREF  
X1  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
REF1  
FS1  
FS0  
Brookdale and Brookdale -G chipset with P4 processor.  
Output Features:  
X2  
GND  
CPU_STOP#*  
CPUCLKT0  
CPUCLKC0  
VDDCPU  
CPUCLKT1  
CPUCLKC1  
GND  
VDDCPU  
CPUCLKT2  
CPUCLKC2  
MULTSEL0*  
I REF  
•
•
•
•
•
•
3 - Pairs of differential CPU clocks (differential current mode)  
5 - 3V66 @ 3.3V  
10 - PCI @ 3.3V  
2 - 48MHz @ 3.3V fixed  
1 - REF @ 3.3V, 14.318MHz  
1PCICLK_F0  
1PCICLK_F1  
PCICLK_F2  
VDDPCI  
GND  
1*WDEN/PCICLK0  
PCICLK1  
PCICLK2  
PCICLK3  
VDDPCI  
GND  
1 - VCH/3V66 @ 3.3V, 48 MHz or 66.6 MHz  
Features/Benefits:  
•
•
•
•
•
•
Programmable output frequency.  
Programmable output divider ratios.  
Programmable output rise/fall time.  
PCICLK4  
PCICLK5  
PCICLK6  
VDD3V66  
GND  
3V66_2  
3V66_3  
3V66_4  
3V66_5  
GND  
FS2  
48MHz_USB/FS3**  
48MHz_DOT  
AVDD48  
GND  
3V66_1/VCH_CLK/FS4**  
PCI_STOP#*  
3V66_0  
VDD  
GND  
SCLK  
SDATA  
Programmable output skew.  
Programmable spread percentage for EMI control.  
Watchdog timer technology to reset system  
if system malfunctions.  
*PD#  
VDDA  
GND  
*Vtt_PWRGD#  
•
•
•
Programmable watch dog safe frequency.  
Support I2C Index read/write and block read/write operations.  
Uses external 14.318MHz crystal.  
56-Pin 300-mil SSOP & 240-milTSSOP  
1. These outputs have 2X drive strength.  
* Internal Pull-up resistor of 120K to VDD  
Key Specifications:  
•
•
•
CPU Output Jitter <150ps  
3V66 Output Jitter <250ps  
CPU Output Skew <100ps  
** these inputs have 120K internal pull-down  
to GND  
Frequency Table  
Block Diagram  
CPUCLK 3V66 PCICLK  
FS4 FS3 FS2 FS1 FS0  
MHz  
MHz  
MHz  
PLL2  
48MHz_USB  
48MHz_DOT  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
66.66*  
100.00  
200.00  
133.33  
100.90  
105.00  
109.00  
114.00  
117.00  
127.00  
130.00  
132.50  
205.00  
170.00  
180.00  
190.00  
66.66  
66.66  
66.66  
66.66  
67.27  
70.00  
72.67  
76.00  
78.00  
72.86  
74.29  
75.71  
70.00  
56.67  
60.00  
63.33  
33.33  
33.33  
33.33  
33.33  
33.63  
35.00  
36.33  
38.00  
39.00  
36.43  
37.14  
37.89  
35.00  
28.33  
30.00  
31.67  
X1  
X2  
XTAL  
OSC  
3V66_1/VCH_CLK  
REF  
PLL1  
Spread  
Spectrum  
CPUCLKT (2:0)  
CPUCLKC (2:0)  
CPU  
DIVDER  
3
Stop  
Stop  
3
PCI  
DIVDER  
PCICLK (6:0)  
7
3
WDEN  
PD#  
PCICLK_F (2:0)  
Control  
Logic  
CPU_STOP#  
PCI_STOP#  
MULTSEL0  
FS (4:0)  
3V66  
3V66 (5:2, 0)  
I REF  
DIVDER  
5
Config.  
Reg.  
SDATA  
SCLK  
Vtt_PWRGD#  
For additional frequency selections please refer to Byte 0.  
* For 950211BF version, this frequency is 166.66MHz.  
Power Groups  
VDDA = Analog Core PLL  
VDDREF = REF, Xtal  
AVDD48 = 48MHz  
0465D—05/05/04  
1234567...20

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