Datasheet > 存储 > EEPROM> 93C56A-I/OTG

93C56A-I/OTG

更新时间： 2024-01-07 14:01:53

品牌	Logo	应用领域
美国微芯 - MICROCHIP		可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
12页	169K
描述
256 X 8 MICROWIRE BUS SERIAL EEPROM, PDSO6, LEAD FREE, PLASTIC, SC-74A, SOT-23, 6 PIN

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技术参数
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93C56A-I/OTG 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	0.150 INCH, PLASTIC, SOIC-8	针数：	8
Reach Compliance Code：	unknown	Factory Lead Time：	6 weeks
风险等级：	5.65	其他特性：	10K ERASE/WRITE CYCLES MIN; DATA RETENTION > 40 YEARS
备用内存宽度：	16	最大时钟频率 (fCLK)：	2 MHz
数据保留时间-最小值：	40	耐久性：	1000000 Write/Erase Cycles
JESD-30 代码：	R-PDSO-G8	JESD-609代码：	e0
内存密度：	2048 bit	内存集成电路类型：	EEPROM
内存宽度：	8	功能数量：	1
端子数量：	8	字数：	256 words
字数代码：	256	工作模式：	SYNCHRONOUS
最高工作温度：	125 °C	最低工作温度：	-40 °C
组织：	256X8	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP8,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	并行/串行：	SERIAL
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	5 V
认证状态：	Not Qualified	串行总线类型：	MICROWIRE
最大待机电流：	0.0001 A	子类别：	EEPROMs
最大压摆率：	0.004 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	AUTOMOTIVE	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
最长写入周期时间 (tWC)：	1 ms	写保护：	SOFTWARE
Base Number Matches：	1

93C56A-I/OTG 数据手册

93C56A/B

CLK cycles are not required during the self-timed

WRITE (i.e., auto ERASE/WRITE) cycle.

2.0

PIN DESCRIPTION

2.1

Chip Select (CS)

After detecting a START condition, the speciﬁed num-

ber of clock cycles (respectively low to high transitions

of CLK) must be provided. These clock cycles are

required to clock in all required opcode, address, and

data bits before an instruction is executed (Table 2-1

and Table 2-2). CLK and DI then become don't care

inputs waiting for a new START condition to be

detected.

A high level selects the device. A low level deselects

the device and forces it into standby mode. However, a

programming cycle which is already in progress will be

completed, regardless of the CS input signal. If CS is

brought low during a program cycle, the device will go

into standby mode as soon as the programming cycle

is completed.

Note: CS must go low between consecutive

CS must be low for 250 ns minimum (TCSL) between

consecutive instructions. If CS is low, the internal con-

trol logic is held in a RESET status.

instructions.

2.3

Data In (DI)

2.2

Serial Clock (CLK)

Data In is used to clock in a START bit, opcode,

address, and data synchronously with the CLK input.

The Serial Clock is used to synchronize the communi-

cation between a master device and the 93C56A/B.

Opcode, address, and data bits are clocked in on the

positive edge of CLK. Data bits are also clocked out on

the positive edge of CLK.

2.4

Data Out (DO)

Data Out is used in the READ mode to output data syn-

chronously with the CLK input (TPD after the positive

edge of CLK).

CLK can be stopped anywhere in the transmission

sequence (at high or low level) and can be continued

anytime with respect to clock high time (TCKH) and

clock low time (TCKL). This gives the controlling master

freedom in preparing opcode, address, and data.

This pin also provides READY/BUSY status informa-

tion during ERASE and WRITE cycles. READY/BUSY

status information is available on the DO pin if CS is

brought high after being low for minimum chip select

low time (TCSL) and an ERASE or WRITE operation

has been initiated. The status signal is not available on

DO, if CS is held low during the entire ERASE or

WRITE cycle. In this case, DO is in the HIGH-Z mode.

If status is checked after the ERASE/WRITE cycle, the

data line will be high to indicate the device is ready.

CLK is a “Don't Care” if CS is low (device deselected).

If CS is high, but the START condition has not been

detected, any number of clock cycles can be received

by the device without changing its status (i.e., waiting

for a START condition).

TABLE 2-1:

INSTRUCTION SET FOR 93C56A

Instruction SB Opcode

Address

Data In

Data Out

Req. CLK Cycles

A7 A6 A5 A4 A3 A2 A1 A0

—

(RDY/BSY)

HIGH-Z

ERASE

ERAL

EWDS

EWEN

READ

WRITE

WRAL

HIGH-Z

A7 A6 A5 A4 A3 A2 A1 A0

D7 - D0

A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0

(RDY/BSY)

D7 - D0

TABLE 2-2:

INSTRUCTION SET FOR 93C56B

Instruction SB Opcode

Address

Data In

Data Out

Req. CLK Cycles

A6 A5 A4 A3 A2 A1 A0

—

(RDY/BSY)

HIGH-Z

ERASE

ERAL

EWDS

EWEN

READ

WRITE

WRAL

HIGH-Z

A6 A5 A4 A3 A2 A1 A0

D15 - D0

(RDY/BSY)

A6 A5 A4 A3 A2 A1 A0 D15 - D0

D15 - D0

1998 Microchip Technology Inc.

Preliminary

DS21206B-page 4-3

1 234 5 6 7...12

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