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935325511557

更新时间: 2024-11-08 19:59:03
品牌 Logo 应用领域
恩智浦 - NXP 微控制器外围集成电路
页数 文件大小 规格书
52页 1153K
描述
Microcontroller

935325511557 技术参数

生命周期:ActiveReach Compliance Code:unknown
风险等级:5.77uPs/uCs/外围集成电路类型:MICROCONTROLLER
Base Number Matches:1

935325511557 数据手册

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Freescale Semiconductor  
Document Number: MC9S08MM128  
Rev. 3, 10/2010  
Data Sheet: Technical Data  
An Energy-Efficient Solution from Freescale  
MC9S08MM128 series  
Covers: MC9S08MM128, and MC9S08MM64, MC9S08MM32,  
and MC9S08MM32A  
64-LQFP 10mm x 10mm  
80-LQFP 12mm x 12mm  
81-MapBGA 10mm x10mm  
byte-by-byte data transfer; supports broadcast mode and 11-bit  
addressing  
PRACMP — Analog comparator with selectable interrupt;  
compare option to programmable internal reference voltage;  
operation in stop3  
SCI Two serial communications interfaces with optional 13-bit  
break; option to connect Rx input to PRACMP output on SCI1 and  
SCI2; High current drive on Tx on SCI1 and SCI2; wake-up from  
stop3 on Rx edge  
SPI1— Serial peripheral interface (SPI) with 64-bit FIFO buffer;  
16-bit or 8-bit data transfers; full-duplex or single-wire  
bidirectional; double-buffered transmit and receive; master or  
slave mode; MSB-first or LSB-first shifting  
8-Bit HCS08 Central Processor Unit (CPU)  
Up to 48-MHz CPU above 2.4 V, 40 MHz CPU above 2.1 V, and  
20 MHz CPU above 1.8 V across temperature of -40°C to 105°C  
HCS08 instruction set with added BGND instruction  
Support for up to 33 interrupt/reset sources  
On-Chip Memory  
128 K Dual Array Flash read/program/erase over full operating  
voltage and temperature  
12 KB Random-access memory (RAM)  
Security circuitry to prevent unauthorized access to RAM and  
Flash  
Power-Saving Modes  
Two ultra-low power stop modes. Peripheral clock enable register  
can disable clocks to unused modules to reduce currents  
Time of Day (TOD) — Ultra-low power 1/4 sec counter with up to  
64s timeout.  
Ultra-low power external oscillator that can be used in stop modes  
to provide accurate clock source to the TOD. 6 usec typical wake  
up time from stop3 mode  
SPI2— Serial peripheral interface with full-duplex or single-wire  
bidirectional; Double-buffered transmit and receive; Master or  
Slave mode; MSB-first or LSB-first shifting  
TPM Two 4-channel Timer/PWM Module; Selectable input  
capture, output compare, or buffered edge- or center-aligned  
PWM on each channel; external clock input/pulse accumulator  
USB — Supports USB in full-speed device configuration. On-chip  
transceiver and 3.3V regulator help save system cost, fully  
compliant with USB Specification 2.0. Allows control, bulk,  
interrupt and isochronous transfers. Not available on  
MC9S08MM32A devices.  
Clock Source Options  
Oscillator (XOSC1) — Loop-control Pierce oscillator; 32.768 kHz  
crystal or ceramic resonator dedicated for TOD operation.  
Oscillator (XOSC2) — for high frequency crystal input for MCG  
reference to be used for system clock and USB operations.  
Multipurpose Clock Generator (MCG) — PLL and FLL; precision  
trimming of internal reference allows 0.2% resolution and 2%  
deviation over temperature and voltage; supports CPU  
frequencies from 4 kHz to 48 MHz.  
ADC16 — 16-bit Successive approximation ADC with up to 4  
dedicated differential channels and 8 single-ended channels;  
range compare function; 1.7 mV/C temperature sensor; internal  
bandgap reference channel; operation in stop3; fully functional  
from 3.6V to 1.8V, Configurable hardware trigger for 8 Channel  
select and result registers  
PDB — Programmable delay block with 16-bit counter and  
modulus and prescale to set reference clock to bus divided by 1 to  
bus divided by 2048; 8 trigger outputs for ADC16 module provides  
periodic coordination of ADC sampling sequence with sequence  
completion interrupt; Back-to-Back mode and Timed mode  
System Protection  
Watchdog computer operating properly (COP) reset Watchdog  
computer operating properly (COP) reset with option to run from  
dedicated 1-kHz internal clock source or bus clock  
Low-voltage detection with reset or interrupt; selectable trip points;  
separate low-voltage warning with optional interrupt; selectable  
trip points  
Illegal opcode and illegal address detection with reset  
Flash block protection for each array to prevent accidental  
write/erasure  
DAC  
12-bit resolution; 16-word data buffers with configurable  
watermark  
.
OPAMP Two flexible operational amplifiers configurable for  
general operations; Low offset and temperature drift.  
TRIAMP Two trans-impedance amplifiers dedicated for  
converting current inputs into voltages.  
Hardware CRC to support fast cyclic redundancy checks  
Development Support  
Single-wire background debug interface  
Input/Output  
Real-time debug with 6 hardware breakpoints (4 PC, 1 address  
and 1 data) Breakpoint capability to allow single breakpoint setting  
during in-circuit debugging  
On-chip in-circuit emulator (ICE) debug module containing 3  
comparators and 9 trigger modes  
Up to 47 GPIOs and 2 output-only pin and 1 input-only pin.  
Voltage Reference output (VREFO).  
Dedicated infrared output pin (IRO) with  
high current sink capability.  
Up to 16 KBI pins with selectable polarity.  
Peripherals  
Package Options  
CMT— Carrier Modulator timer for remote control  
81-MBGA 10x10 mm  
80-LQFP 12x12 mm  
64-LQFP 10x10 mm  
communications. Carrier generator, modulator and driver for  
dedicated infrared out. Can be used as an output compare timer.  
IIC— Up to 100 kbps with maximum bus loading; Multi-master  
operation; Programmable slave address; Interrupt driven  
Freescale reserves the right to change the detail specifications as may be required to permit  
improvements in the design of its products.  
© Freescale Semiconductor, Inc., 2009-2010. All rights reserved.  
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.  

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