PIN CONNECTIONS
3.2
Pin definitions
Table 2. PF0200 pin definitions
Pin
number
Pin
function
Pin name
Max rating
Type
Definition
Open drain interrupt signal to processor
1
2
INTB
O
O
3.6 V
3.6 V
Digital
Digital
SDWNB
Open drain signal to indicate an imminent system shutdown
Open drain reset output to processor. Alternatively can be used as a Power Good
output.
3
4
5
RESETBMCU
STANDBY
ICTEST
O
I
3.6 V
3.6 V
7.5 V
Digital
Digital
Standby input signal from processor
Digital/
Analog
I
Reserved pin. Connect to GND in application.
Output voltage feedback for SW1A/B. Route this trace separately from the high-
current path and terminate at the output capacitance.
6
7
SW1FB (4)
SW1AIN (4)
I
I
3.6 V
4.8 V
Analog
Analog
Input to SW1A regulator. Bypass with at least a 4.7 μF ceramic capacitor and a
0.1 μF decoupling capacitor as close to the pin as possible.
8
9
SW1ALX (4)
SW1BLX (4)
O
O
4.8 V
4.8 V
Analog
Analog
Regulator 1A switch node connection
Regulator 1B switch node connection
Input to SW1B regulator. Bypass with at least a 4.7 μF ceramic capacitor and a
0.1 μF decoupling capacitor as close to the pin as possible.
10
SW1BIN (4)
I
4.8 V
Analog
Reserved for pin to pin compatibility. Internally connected. Leave this pin
unconnected.
11
12
13
RSVD1
RSVD2
RSVD3
-
-
-
-
-
-
Reserved
Reserved Reserved for pin to pin compatibility. Connect this pin to VIN.
Reserved for pin to pin compatibility. Internally connected. Leave this pin
unconnected.
Reserved
Ground reference for regulator SW1AB. It is connected externally to GNDREF
through a board ground plane.
14
SW1VSSSNS
GND
-
GND
Ground reference for regulator SW2. It is connected externally to GNDREF, via
board ground plane.
15
16
17
18
19
20
21
GNDREF1
VGEN1
VIN1
GND
-
GND
O
I
2.5 V
Analog
Analog
VGEN1 regulator output, Bypass with a 2.2 μF ceramic output capacitor.
VGEN1, 2 input supply. Bypass with a 1.0 μF decoupling capacitor as close to the
pin as possible.
3.6 V
VGEN2
RSVD4
RSVD5
RSVD6
O
-
2.5 V
Analog
VGEN2 regulator output, Bypass with a 4.7 μF ceramic output capacitor.
Reserved for pin to pin compatibility. Internally connected. Leave this pin
unconnected.
-
-
-
Reserved
-
Reserved Reserved for pin to pin compatibility. Connect this pin to VIN
Reserved for pin to pin compatibility. Internally connected. Leave this pin
unconnected.
-
Reserved
22
23
SW2LX (4)
SW2IN (4)
O
I
4.8 V
4.8 V
Analog
Analog
Regulator 2 switch node connection
Input to SW2 regulator. Connect pin 23 together with pin 24 and bypass with at least
a 4.7 μF ceramic capacitor and a 0.1 μF decoupling capacitor as close to these pins
as possible.
24
SW2IN (4)
I
4.8 V
Analog
Output voltage feedback for SW2. Route this trace separately from the high-current
path and terminate at the output capacitance.
25
26
27
SW2FB (4)
VGEN3
VIN2
I
O
I
3.6 V
3.6 V
3.6 V
Analog
Analog
Analog
VGEN3 regulator output. Bypass with a 2.2 μF ceramic output capacitor.
VGEN3,4 input. Bypass with a 1.0 μF decoupling capacitor as close to the pin as
possible.
PF0200
6
NXP Semiconductors
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