Document Number: MPC8544EEC
Rev. 8, 09/2015
Freescale Semiconductor
Technical Data
MPC8544E PowerQUICC III
Integrated Processor
Hardware Specifications
Contents
1 MPC8544E Overview
This section provides a high-level overview of MPC8544E
features. Figure 1 shows the major functional units within
the device.
1. MPC8544E Overview . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 8
3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 13
4. Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 16
6. DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 16
7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8. Enhanced Three-Speed Ethernet (eTSEC),
1.1
Key Features
MII Management 23
9. Ethernet Management Interface Electrical
The following list provides an overview of the device feature
set:
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
10. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
11. Programmable Interrupt Controller . . . . . . . . . . . . . 55
12. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
13. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
14. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
15. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
16. High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 63
17. PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
18. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 81
19. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
20. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
21. System Design Information . . . . . . . . . . . . . . . . . . 105
22. Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . 114
23. Document Revision History . . . . . . . . . . . . . . . . . . 116
•
High-performance, 32-bit core enhanced by
resources for embedded cores defined by the Power
ISA, and built on Power Architecture® technology:
— 32-Kbyte L1 instruction cache and 32-Kbyte L1
data cache with parity protection. Caches can be
locked entirely or on a per-line basis, with
separate locking for instructions and data.
— Signal-processing engine (SPE) APU (auxiliary
processing unit). Provides an extensive
instruction set for vector (64-bit) integer and
fractional operations. These instructions use both
the upper and lower words of the 64-bit GPRs as
they are defined by the SPE APU.
Freescale reserves the right to change the detail specifications as may be required
to permit improvements in the design of its products.
© 2008-2011, 2014-2015 Freescale Semiconductor, Inc. All rights reserved.
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