INTERNAL BLOCK DIAGRAM
2
Internal block diagram
SW1FB
VGEN1
100 mA
VIN1
PF0200
SW1AIN
SW1ALX
VGEN1
O/P
Drive
SW1A/B
Single/Dual
2500 mA
Buck
VGEN2
250 mA
VGEN2
SW1BLX
SW1BIN
O/P
Drive
VIN2
VGEN3
100 mA
SW1VSSSNS
VGEN3
VGEN4
350 mA
VGEN4
SW2LX
SW2IN
O/P
Drive
SW2
1500 mA
Buck
Core Control logic
VIN3
VGEN5
100 mA
SW2IN
VGEN5
SW2FB
GNDREF1
Initialization State Machine
VGEN6
200 mA
VGEN6
Supplies
Control
OTP
SW3AFB
SW3AIN
SW3ALX
O/P
Drive
VDDOTP
VDDIO
SW3A/B
Single Phase
2500 mA
Buck
CONTROL
I2C
Interface
SW3BLX
SW3BIN
O/P
Drive
SCL
SDA
DVS CONTROL
SW3BFB
DVS Control
SW3VSSSNS
I2C Register
map
Trim-In-Package
SWBSTLX
VCOREDIG
VCOREREF
SWBST
600 mA
Boost
O/P
Drive
SWBSTIN
SWBSTFB
Reference
Generation
Clocks and
resets
VCORE
GNDREF
VREFDDR
VINREFDDR
Clocks
32 kHz and 16 MHz
VHALF
VIN
Best
of
Supply
Li Cell
Charger
LICELL
VSNVS
Figure 2. PF0200 simplified internal block diagram
PF0200
4
NXP Semiconductors