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935297796115 PDF预览

935297796115

更新时间: 2024-11-07 19:29:03
品牌 Logo 应用领域
恩智浦 - NXP 输入元件光电二极管逻辑集成电路
页数 文件大小 规格书
19页 324K
描述
AUP/ULP/V SERIES, DUAL 1-INPUT INVERT GATE, PDSO6, 1 X 1.45 MM, 0.50 MM HEIGHT, 0.50 MM PITCH, PLASTIC, SOT-886, MO-252, XSON-6

935297796115 技术参数

生命周期:Transferred包装说明:VSON,
Reach Compliance Code:unknown风险等级:5.6
系列:AUP/ULP/VJESD-30 代码:R-PDSO-N6
JESD-609代码:e3长度:1.45 mm
逻辑集成电路类型:INVERTER功能数量:2
输入次数:1端子数量:6
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:VSON
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, VERY THIN PROFILE
传播延迟(tpd):20.9 ns座面最大高度:0.5 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):0.8 V
标称供电电压 (Vsup):1.1 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:TIN端子形式:NO LEAD
端子节距:0.5 mm端子位置:DUAL
宽度:1 mmBase Number Matches:1

935297796115 数据手册

 浏览型号935297796115的Datasheet PDF文件第2页浏览型号935297796115的Datasheet PDF文件第3页浏览型号935297796115的Datasheet PDF文件第4页浏览型号935297796115的Datasheet PDF文件第5页浏览型号935297796115的Datasheet PDF文件第6页浏览型号935297796115的Datasheet PDF文件第7页 
74AUP2G3404  
Low-power buffer and inverter  
Rev. 1 — 22 August 2012  
Product data sheet  
1. General description  
The 74AUP2G3404 is a single buffer and single inverter.  
Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall  
times across the entire VCC range from 0.8 V to 3.6 V.  
This device ensures a very low static and dynamic power consumption across the entire  
VCC range from 0.8 V to 3.6 V.  
This device is fully specified for partial power-down applications using IOFF. The IOFF  
circuitry disables the output, preventing the damaging backflow current through the device  
when it is powered down.  
2. Features and benefits  
Wide supply voltage range from 0.8 V to 3.6 V  
High noise immunity  
Complies with JEDEC standards:  
JESD8-12 (0.8 V to 1.3 V)  
JESD8-11 (0.9 V to 1.65 V)  
JESD8-7 (1.2 V to 1.95 V)  
JESD8-5 (1.8 V to 2.7 V)  
JESD8-B (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114F Class 3A exceeds 5000 V  
MM JESD22-A115-A exceeds 200 V  
CDM JESD22-C101E exceeds 1000 V  
Low static power consumption; ICC = 0.9 A (maximum)  
Latch-up performance exceeds 100 mA per JESD 78 Class II  
Inputs accept voltages up to 3.6 V  
Low noise overshoot and undershoot < 10 % of VCC  
IOFF circuitry provides partial power-down mode operation  
Multiple package options  
Specified from 40 C to +85 C and 40 C to +125 C  

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