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935286883132

更新时间： 2024-11-25 19:53:19
品牌 Logo 应用领域
恩智浦 - NXP 驱动光电二极管接口集成电路驱动器
页数 文件大小 规格书
17页 179K
描述
LINE DRIVER, PDSO10, 1 X 1 MM, 0.5 MM HEIGHT, PLASTIC, SOT1081-1, SON-10

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935286883132 技术参数

生命周期：Obsolete包装说明：VSON,
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.74
差分输出：NO驱动器位数：1
输入特性：SCHMITT TRIGGER接口集成电路类型：LINE DRIVER
接口标准：GENERAL PURPOSEJESD-30 代码：S-PDSO-N10
长度：1.7 mm功能数量：1
端子数量：10最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：VSON封装形状：SQUARE
封装形式：SMALL OUTLINE, VERY THIN PROFILE座面最大高度：0.5 mm
最大供电电压：3.6 V最小供电电压：1.1 V
标称供电电压：1.65 V表面贴装：YES
温度等级：INDUSTRIAL端子形式：NO LEAD
端子节距：0.35 mm端子位置：DUAL
最大传输延迟：6.7 ns宽度：1 mm
Base Number Matches：1

935286883132 数据手册

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74AUP2T1326  
Low-power dual supply buffer/line driver; 3-state  
Rev. 2 — 3 July 2012  
Product data sheet  
1. General description  
The 74AUP2T1326 is a high-performance, dual supply, low-power, low-voltage, dual  
buffer/line driver with output enable circuitry.  
The 74AUP2T1326 is designed for logic-level translation and combines the functions of  
the 74AUP1G32 and 74AUP2G126. The buffer/line driver is controlled by two output  
enable inputs (1OE and 2OE). A logic LOW on input 1OE causes the output 2Y to assume  
a high-impedance OFF-state, a logic LOW on 2OE causes the output 3Y to assume a  
high-impedance OFF-state. The output 1Y is the result of a logic OR of the two output  
enable inputs.  
The output enable inputs (1OE and 2OE) are Schmitt trigger inputs, they switch at  
different voltages for positive and negative-going signals. The difference between the  
positive voltage VT+ and the negative voltage VTis defined as the input hysteresis  
voltage VH. The output enable inputs accept standard input signals and are capable of  
transforming slowly changing input signals into sharply defined, jitter-free output signals  
Both VCC(A) and VCC(B) can be supplied at any voltage between 1.1 V and 3.6 V making  
the device suitable for interfacing between any of the low voltage nodes (1.2 V, 1.5 V,  
1.8 V, 2.5 V and 3.3 V) with compatible input levels. Pins 1OE, 2OE and 1Y are  
referenced to VCC(A) and pins A, 2Y and 3Y are referenced to VCC(B)  
.
The device ensures low static and dynamic power consumption and is fully specified for  
partial power down applications using IOFF. The IOFF circuitry disables the outputs,  
preventing any damaging backflow current through the device when it is powered down.  
2. Features and benefits  
Wide supply voltage range:  
VCC(A): 1.1 V to 3.6 V; VCC(B): 1.1 V to 3.6 V.  
High noise immunity  
Complies with JEDEC standards:  
JESD8-7 (1.2 V to 1.95 V)  
JESD8-5 (1.8 V to 2.7 V)  
JESD8-B (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114F Class 2A exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
CDM JESD22-C101E exceeds 1000 V  
Low static power consumption; ICC = 0.9 A (maximum)  
Latch-up performance exceeds 100 mA per JESD 78 Class II  
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