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935286924118 PDF预览

935286924118

更新时间: 2024-11-25 19:35:35
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
24页 144K
描述
HC/UH SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO20, PLASTIC, TSSOP1-20

935286924118 技术参数

生命周期:Obsolete包装说明:TSSOP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.67其他特性:HOLD MODE; COMMON I/O PINS; TOTEMPOLE SERIAL SHIFT RIGHT & SHIFT LEFT OUTPUTS; GATED OUTPUT CONTROL
计数方向:BIDIRECTIONAL系列:HC/UH
JESD-30 代码:R-PDSO-G20长度:6.5 mm
逻辑集成电路类型:PARALLEL IN PARALLEL OUT位数:8
功能数量:1端子数量:20
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟(tpd):60 ns座面最大高度:1.1 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL触发器类型:POSITIVE EDGE
宽度:4.4 mm最小 fmax:17 MHz
Base Number Matches:1

935286924118 数据手册

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74HC299; 74HCT299  
8-bit universal shift register; 3-state  
Rev. 03 — 28 July 2008  
Product data sheet  
1. General description  
The 74HC299; 74HCT299 are high-speed Si-gate CMOS devices which are  
pin-compatible with Low-power Schottky TTL (LSTTL) devices. They are specified in  
compliance with JEDEC standard no. 7A.  
The 74HC299; 74HCT299 contain eight edge-triggered D-type flip-flops and the  
interstage logic necessary to perform synchronous shift-right, shift-left, parallel load and  
hold operations. An operation is determined by the mode select inputs S0 and S1, as  
shown in Table 3.  
Pins I/O0 to I/O7 are flip-flop 3-state buffer outputs which allow them to operate as data  
inputs in parallel load mode. The serial outputs Q0 and Q7 are used for expansion in  
serial shifting of longer words.  
A LOW signal on the asynchronous master reset input MR overrides the Sn and clock CP  
inputs and resets the flip-flops. All other state changes are initiated by the rising edge of  
the clock pulse. Inputs can change when the clock is in either state, provided that the  
recommended set-up and hold times are observed.  
A HIGH signal on the 3-state output enable inputs OE1 or OE2 disables the 3-state  
buffers and the I/On outputs are set to the high-impedance OFF-state. In this condition,  
the shift, hold, load and reset operations still occur when preparing for a parallel load  
operation. The 3-state buffers are also disabled by HIGH signals on both S0 and S1.  
2. Features  
I Multiplexed inputs/outputs provide improved bit density  
I Four operating modes:  
N Shift left  
N Shift right  
N Hold (store)  
N Load data  
I Operates with output enable or at high-impedance OFF-state (Z)  
I 3-state outputs drive bus lines directly  
I Cascadable for n-bit word lengths  
I ESD protection:  
N HBM JESD22-A114E exceeds 2000 V  
N MM JESD22-A115-A exceeds 200 V  
I Specified from 40 °C to +85 °C and from 40 °C to +125 °C  

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