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935284594112

更新时间： 2024-11-25 20:05:19
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
25页 162K
描述
AVC SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24, 4.40 MM, PLASTIC, MO-153, SOT355-1, TSSOP-24

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935284594112 技术参数

生命周期：Transferred包装说明：TSSOP,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.68系列：AVC
JESD-30 代码：R-PDSO-G24JESD-609代码：e4
长度：7.8 mm逻辑集成电路类型：BUS TRANSCEIVER
位数：8功能数量：1
端口数量：2端子数量：24
最高工作温度：125 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟（tpd）：9.9 ns座面最大高度：1.1 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：0.8 V
标称供电电压 (Vsup)：1.1 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子面层：NICKEL PALLADIUM GOLD端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
宽度：4.4 mmBase Number Matches：1

935284594112 数据手册

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74AVCH8T245  
8-bit dual supply translating transceiver with configurable  
voltage translation; 3-state  
Rev. 5 — 27 December 2012  
Product data sheet  
1. General description  
The 74AVCH8T245 is an 8-bit, dual supply transceiver that enables bidirectional level  
translation. It features two 8-bit input-output ports (An and Bn), a direction control input  
(DIR), a output enable input (OE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A)  
and VCC(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device  
suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V,  
2.5 V and 3.3 V). Pins An, OE and DIR are referenced to VCC(A) and pins Bn are  
referenced to VCC(B). A HIGH on DIR allows transmission from An to Bn and a LOW on  
DIR allows transmission from Bn to An. The output enable input (OE) can be used to  
disable the outputs so the buses are effectively isolated.  
The device is fully specified for partial power-down applications using IOFF. The IOFF  
circuitry disables the output, preventing any damaging backflow current through the  
device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at  
GND level, both An and Bn outputs are in the high-impedance OFF-state. The bus-hold  
circuitry on the powered-up side always stays active.  
The 74AVCH8T245 has active bus hold circuitry which is provided to hold unused or  
floating data inputs at a valid logic level. This feature eliminates the need for external  
pull-up or pull-down resistors.  
2. Features and benefits  
Wide supply voltage range:  
VCC(A): 0.8 V to 3.6 V  
VCC(B): 0.8 V to 3.6 V  
Complies with JEDEC standards:  
JESD8-12 (0.8 V to 1.3 V)  
JESD8-11 (0.9 V to 1.65 V)  
JESD8-7 (1.2 V to 1.95 V)  
JESD8-5 (1.8 V to 2.7 V)  
JESD8-B (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114E Class 3B exceeds 8000 V  
MM JESD22-A115-A exceeds 200 V  
CDM JESD22-C101C exceeds 1000 V  
Maximum data rates:  
380 Mbit/s (1.8 V to 3.3 V translation)  
260 Mbit/s (1.1 V to 3.3 V translation)  
1234567...25

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