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935054480623

更新时间： 2024-11-10 19:58:35
品牌 Logo 应用领域
恩智浦 - NXP 驱动信息通信管理光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
6页 69K
描述
IC ABT SERIES, 10 1-BIT DRIVER, TRUE OUTPUT, PDSO24, PLASTIC, SO-24, Bus Driver/Transceiver

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935054480623 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOP,
针数：24Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.44
系列：ABTJESD-30 代码：R-PDSO-G24
JESD-609代码：e4逻辑集成电路类型：BUS DRIVER
湿度敏感等级：1位数：1
功能数量：10端口数量：2
端子数量：24最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
传播延迟（tpd）：6.7 ns认证状态：Not Qualified
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：BICMOS温度等级：INDUSTRIAL
端子面层：NICKEL PALLADIUM GOLD端子形式：GULL WING
端子位置：DUAL处于峰值回流温度下的最长时间：30
Base Number Matches：1

935054480623 数据手册

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Philips Semiconductors  
Product specification  
10-bit D-type flip-flop; positive-edge trigger  
(3-State)  
74ABT821  
extra data width for wider data/address paths of buses carrying  
parity.  
FEATURES  
• High speed parallel registers with positive edge-triggered D-type  
flip-flops  
The 74ABT821 is a buffered 10-bit wide version of the  
74ABT374/74ABT534 functions.  
• Ideal where high speed, light loading, or increased fan-in are  
required with MOS microprocessors  
The 74ABT821 is a 10-bit, edge triggered register coupled to ten  
3-State output buffers. The two sections of the device are controlled  
independently by the clock (CP) and Output Enable (OE) control  
gates.  
• Output capability: +64mA/–32mA  
• Latch-up protection exceeds 500mA per Jedec Std 17  
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015  
The register is fully edge triggered. The state of each D input, one  
set-up time before the Low-to-High clock transition is transferred to  
the corresponding flip-flop’s Q output.  
and 200 V per Machine Model  
• Power-up 3-State  
• Power-up Reset  
The 3-State output buffers are designed to drive heavily loaded  
3-State buses, MOS memories, or MOS microprocessors.  
DESCRIPTION  
The active Low Output Enable (OE) controls all ten 3-State buffers  
independent of the register operation. When OE is Low, the data in  
the register appears at the outputs. When OE is High, the outputs  
are in high impedance ”off” state, which means they will neither drive  
nor load the bus.  
The 74ABT821 high-performance BiCMOS device combines low  
static and dynamic power dissipation with high speed and high  
output drive.  
The 74ABT821 Bus interface Register is designed to eliminate the  
extra packages required to buffer existing registers and provide  
QUICK REFERENCE DATA  
CONDITIONS  
= 25°C; GND = 0V  
SYMBOL  
PARAMETER  
TYPICAL  
UNIT  
T
amb  
t
t
Propagation delay  
CP to Qn  
PLH  
PHL  
C = 50pF; V = 5V  
4.6  
ns  
L
CC  
C
Input capacitance  
Output capacitance  
Total supply current  
V = 0V or V  
CC  
4
7
pF  
pF  
nA  
IN  
I
C
Outputs disabled; V = 0V or V  
O CC  
OUT  
CCZ  
I
Outputs disabled; V =5.5V  
500  
CC  
ORDERING INFORMATION  
PACKAGES  
TEMPERATURE RANGE OUTSIDE NORTH AMERICA  
NORTH AMERICA  
74ABT821 N  
DWG NUMBER  
SOT222-1  
24-Pin Plastic DIP  
–40°C to +85°C  
–40°C to +85°C  
–40°C to +85°C  
–40°C to +85°C  
74ABT821 N  
74ABT821 D  
74ABT821 DB  
74ABT821 PW  
24-Pin plastic SO  
74ABT821 D  
SOT137-1  
24-Pin Plastic SSOP Type II  
24-Pin Plastic TSSOP Type I  
74ABT821 DB  
74ABT821PW DH  
SOT340-1  
SOT355-1  
PIN CONFIGURATION  
PIN DESCRIPTION  
PIN NUMBER  
SYMBOL  
FUNCTION  
24  
Output enable input  
(active-Low)  
OE  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
1
2
3
4
5
6
7
8
9
V
CC  
1
OE  
23 Q0  
22 Q1  
21 Q2  
20 Q3  
19 Q4  
18 Q5  
17 Q6  
16 Q7  
2, 3, 4, 5, 6,  
7, 8, 9, 10, 11  
D0-D9  
Q0-Q9  
Data inputs  
23, 22, 21, 20, 19,  
18, 17, 16, 15, 14  
Data outputs  
Clock pulse input (active  
rising edge)  
TOP VIEW  
13  
CP  
10  
20  
GND  
Ground (0V)  
V
CC  
Positive supply voltage  
D8 10  
D9 11  
15  
14  
13  
Q8  
Q9  
CP  
GND 12  
SA00223  
1
1995 Sep 06  
853-1616 15703  
123456

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