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9084901MCA PDF预览

9084901MCA

更新时间： 2024-11-21 03:13:07
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器逻辑集成电路
页数 文件大小 规格书
15页 452K
描述
Dual J-K Flip-Flop with Reset Negative-Edge Trigger

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中文翻译

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9084901MCA 技术参数

是否无铅：含铅生命周期：Obsolete
零件包装代码：DIP包装说明：DIP,
针数：14Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.84
Is Samacsys：N系列：HC/UH
JESD-30 代码：R-GDIP-T14逻辑集成电路类型：J-K FLIP-FLOP
位数：2功能数量：2
端子数量：14最高工作温度：125 °C
最低工作温度：-55 °C输出极性：COMPLEMENTARY
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装形状：RECTANGULAR封装形式：IN-LINE
传播延迟（tpd）：65 ns认证状态：Not Qualified
筛选级别：MIL-STD-883座面最大高度：5.08 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL触发器类型：NEGATIVE EDGE
宽度：7.62 mm最小 fmax：19 MHz
Base Number Matches：1

9084901MCA 数据手册

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CD54HC107, CD74HC107,  
CD74HCT107  
Data sheet acquired from Harris Semiconductor  
SCHS139D  
Dual J-K Flip-Flop with Reset  
Negative-Edge Trigger  
March 1998 - Revised October 2003  
Features  
Description  
• Hysteresis on Clock Inputs for Improved Noise Immu-  
nity and Increased Input Rise and Fall Times  
The ’HC107 and CD74HCT107 utilize silicon gate CMOS  
technology to achieve operating speeds equivalent to LSTTL  
parts. They exhibit the low power consumption of standard  
CMOS integrated circuits, together with the ability to drive 10  
LSTTL loads.  
[ /Title  
(CD74  
HC107  
,
CD74  
HCT10  
7)  
/Sub-  
ject  
(Dual  
J-K  
Flip-  
Flop  
with  
Reset  
Nega-  
tive-  
• Asynchronous Reset  
• Complementary Outputs  
• Buffered Inputs  
These flip-flops have independent J, K, Reset and Clock  
inputs and Q and Q outputs. They change state on the  
negative-going transition of the clock pulse. Reset is  
accomplished asynchronously by a low level input.  
• Typical f  
MAX  
= 60MHz at V = 5V, C = 15pF,  
CC L  
o
T = 25 C  
A
• Fanout (Over Temperature Range)  
This device is functionally identical to the HC/HCT73 but  
differs in terminal assignment and in some parametric limits.  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
The HCT logic family is functionally as well as pin compatible  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C with the standard LS family.  
• Balanced Propagation Delay and Transition Times  
Ordering Information  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
TEMP. RANGE  
o
PART NUMBER  
CD54HC107F3A  
CD74HC107E  
( C)  
PACKAGE  
14 Ld CERDIP  
14 Ld PDIP  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
14 Ld PDIP  
• HC Types  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
CD74HC107M  
at V  
= 5V  
CC  
CD74HC107MT  
CD74HC107M96  
CD74HCT107E  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel. The suffix T denotes a small-quantity reel of  
250.  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
OL OH  
l
Pinout  
CD54HC107 (CERDIP)  
CD74HC107 (PDIP, SOIC)  
CD74HCT107 (PDIP)  
TOP VIEW  
1J  
1Q  
1
2
3
4
5
6
7
14 V  
CC  
13 1R  
12 1CP  
11 2K  
10 2R  
1Q  
1K  
2Q  
2Q  
9
8
2CP  
2J  
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
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