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8N4S270AC-1080CDI PDF预览

8N4S270AC-1080CDI

更新时间: 2024-01-27 11:07:02
品牌 Logo 应用领域
艾迪悌 - IDT 机械输出元件振荡器
页数 文件大小 规格书
18页 606K
描述
LVDS Output Clock Oscillator

8N4S270AC-1080CDI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:ActiveReach Compliance Code:compliant
风险等级:5.71其他特性:ENABLE/DISABLE FUNCTION; DIFFERENTIAL OUTPUT; TRAY
最长下降时间:0.45 ns频率调整-机械:NO
频率稳定性:100%JESD-609代码:e3
安装特点:SURFACE MOUNT标称工作频率:125 MHz
最高工作温度:85 °C最低工作温度:-40 °C
振荡器类型:LVDS物理尺寸:7.0mm x 5.0mm x 1.55mm
最长上升时间:0.45 ns最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES最大对称度:53/47 %
端子面层:Matte Tin (Sn)Base Number Matches:1

8N4S270AC-1080CDI 数据手册

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IDT8N4S270 Data Sheet  
LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR  
Power Considerations  
This section provides information on power dissipation and junction temperature for the IDT8N4S270.   
Equations and example calculations are also provided.  
1. Power Dissipation.  
The total power dissipation for the IDT8N4S270 is the sum of the core power plus the power dissipated due to the load. The following is the  
power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.  
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 160mA = 554.4mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The  
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond  
wire and bond pad temperature remains below 125°C.  
The equation for Tj is as follows: Tj = JA * Pd_total + TA  
Tj = Junction Temperature  
JA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and  
a multi-layer board, the appropriate value is 49.4°C/W per Table 6 below.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C + 0.554W * 49.4°C/W = 112.4°C. This is below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of  
board (multi-layer).  
Table 6. Thermal Resistance JA for 6 Lead Ceramic 5mm x 7mm Package, Forced Convection  
JA by Velocity  
Meters per Second  
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards  
49.4°C/W  
44.2°C/W  
42.1°C/W  
IDT8N4S270CCD REVISION A AUGUST 31, 2012  
13  
©2012 Integrated Device Technology, Inc.  

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