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89HPES12N3AZCBCI PDF预览

89HPES12N3AZCBCI

更新时间： 2024-02-27 11:52:59
品牌 Logo 应用领域
艾迪悌 - IDT 时钟PC外围集成电路
页数 文件大小 规格书
31页 555K
描述
PCI Bus Controller, PBGA324, 19 X 19 MM, 1 MM PITCH, CABGA-324

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89HPES12N3AZCBCI 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：BGA
包装说明：19 X 19 MM, 1 MM PITCH, CABGA-324针数：324
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.13
其他特性：ALSO REQUIRES 3.3V SUPPLY地址总线宽度：
总线兼容性：PCI最大时钟频率：125 MHz
外部数据总线宽度：JESD-30 代码：S-PBGA-B324
JESD-609代码：e0长度：19 mm
湿度敏感等级：3端子数量：324
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装等效代码：BGA324,18X18,40封装形状：SQUARE
封装形式：GRID ARRAY, LOW PROFILE峰值回流温度（摄氏度）：225
电源：1,3.3 V认证状态：Not Qualified
座面最大高度：1.5 mm子类别：Bus Controllers
最大供电电压：1.1 V最小供电电压：0.9 V
标称供电电压：1 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn63Pb37)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：20宽度：19 mm
uPs/uCs/外围集成电路类型：BUS CONTROLLER, PCIBase Number Matches：1

89HPES12N3AZCBCI 数据手册

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89HPES12N3A  
Data Sheet  
12-lane 3-Port  
PCI Express® Switch  
®
◆
Flexible Architecture with Numerous Configuration Options  
Device Overview  
–
Automatic per port link width negotiation to x4, x2 or x1  
Automatic lane reversal on all ports  
Automatic polarity inversion on all lanes  
The 89HPES12N3A is a member of the IDT PRECISE™ family of  
PCI Express® switching solutions. The PES12N3A is a 12-lane, 3-port  
peripheral chip that performs PCI Express packet switching with a  
feature set optimized for high performance applications such as servers,  
storage, and communications/networking. It provides connectivity and  
switching functions between a PCI Express upstream port and two  
downstream ports and supports switching between downstream ports.  
–
–
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Ability to load device configuration from serial EEPROM  
◆
◆
Legacy Support  
–
–
PCI compatible INTx emulation  
Bus locking  
Highly Integrated Solution  
Features  
–
–
Requires no external components  
Incorporates on-chip internal memory for packet buffering and  
queueing  
Integrates twelve 2.5 Gbps embedded SerDes with 8B/10B  
encoder/decoder (no separate transceivers needed)  
◆
High Performance PCI Express Switch  
–
–
–
–
–
–
–
–
–
Twelve 2.5Gbps PCI Express lanes  
Three switch ports  
–
Upstream port configurable up to x4  
Downstream ports configurable up to x4  
Low-latency cut-through switch architecture  
Support for Max Payload Sizes up to 2048 bytes  
One virtual channel  
◆
Reliability, Availability, and Serviceability (RAS) Features  
–
–
Supports ECRC and Advanced Error Reporting  
Internal end-to-end parity protection on all TLPs ensures data  
integrity even in systems that do not implement end-to-end  
CRC (ECRC)  
Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O  
Compatible with Hot-Plug I/O expanders used on PC and  
server motherboards  
Eight traffic classes  
PCI Express Base Specification Revision 1.1 compliant  
–
–
Block Diagram  
3-Port Switch Core  
Port  
Arbitration  
Scheduler  
Route Table  
Frame Buffer  
Transaction Layer  
Transaction Layer  
Data Link Layer  
Transaction Layer  
Data Link Layer  
Data Link Layer  
Multiplexer/Demultiplexer  
Multiplexer/Demultiplexer  
Multiplexer/Demultiplexer  
Phy  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
Phy  
Logical Logical  
Layer  
Layer  
Phy  
Phy  
Logical  
Layer  
Phy  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
Phy  
Phy  
Phy  
Logical  
Layer  
Logical  
Layer  
Logical Logical  
Layer  
Logical  
Layer  
Layer  
SerDes SerDes  
SerDes  
SerDes  
SerDes SerDes  
SerDes SerDes  
SerDes  
SerDes  
SerDes  
SerDes  
12 PCI Express Lanes  
One x4 Upstream Port and Two x4 Downstream Ports  
Figure 1 Internal Block Diagram  
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.  
1 of 31  
April 9, 2010  
DSC 6922  
© 2010 Integrated Device Technology, Inc.  
1234567...31

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 		12-Lane 3-Port Gen2 PCI Express Switch
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 		12-Lane 3-Port Gen2 PCI Express Switch

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