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89HPES12NT3ZABCG PDF预览

89HPES12NT3ZABCG

更新时间： 2024-02-14 23:25:20
品牌 Logo 应用领域
艾迪悌 - IDT 开关总线控制器微控制器和处理器外围集成电路PC时钟
页数 文件大小 规格书
29页 497K
描述
12-lane 3-Port Non-Transparent PCI Express㈢ Switch

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中文翻译

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89HPES12NT3ZABCG 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：CABGA
包装说明：CABGA-324针数：324
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.18
Samacsys Confidence：3Samacsys Status：Released
Samacsys PartID：11130511Samacsys Pin Count：324
Samacsys Part Category：Integrated CircuitSamacsys Package Category：BGA
Samacsys Footprint Name：BCG324Samacsys Released Date：2020-01-27 13:35:22
Is Samacsys：N地址总线宽度：
总线兼容性：PCI最大时钟频率：125 MHz
外部数据总线宽度：JESD-30 代码：S-PBGA-B324
JESD-609代码：e1长度：19 mm
湿度敏感等级：3端子数量：324
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装等效代码：BGA324,18X18,40封装形状：SQUARE
封装形式：GRID ARRAY, LOW PROFILE峰值回流温度（摄氏度）：260
电源：1,3.3 V认证状态：Not Qualified
座面最大高度：1.5 mm子类别：Bus Controllers
最大供电电压：1.1 V最小供电电压：0.9 V
标称供电电压：1 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：30宽度：19 mm
uPs/uCs/外围集成电路类型：BUS CONTROLLER, PCIBase Number Matches：1

89HPES12NT3ZABCG 数据手册

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89HPES12NT3  
Data Sheet  
Preliminary Information*  
12-lane 3-Port Non-Transparent  
PCI Express® Switch  
®
◆
Flexible Architecture with Numerous Configuration Options  
Device Overview  
–
–
Port arbitration schemes utilizing round robin  
Supports automatic per port link width negotiation (x4, x2, or  
x1)  
The 89HPES12NT3 is a member of the IDT PRECISE™ family of  
PCI Express® switching solutions offering the next-generation I/O inter-  
connect standard. The PES12NT3 is a 12-lane, 3-port peripheral chip  
that performs PCI Express Base switching with a feature set optimized  
for high performance applications such as servers, storage, and commu-  
nications/networking. It provides high-performance I/O connectivity and  
switching functions between a PCIe® upstream port, a transparent  
downstream port, and a non-transparent downstream port.  
–
–
–
Static lane reversal on all ports  
Automatic polarity inversion on all lanes  
Supports locked transactions, allowing use with legacy soft-  
ware  
–
–
Ability to load device configuration from serial EEPROM  
Ability to control device via SMBus  
◆
Non-Transparent Port  
With non-transparent bridging (NTB) functionality, the PES12NT3  
can be used standalone or as a chipset with IDT PCIe System Intercon-  
nect Switches in multi-host and intelligent I/O applications such as  
communications, storage, and blade servers where inter-domain  
communication is required.  
–
–
Crosslink support on NTB port  
Four mapping windows supported  
• Each may be configured as a 32-bit memory or I/O window  
• May be paired to form a 64-bit memory window  
Interprocessor communication  
–
• Thirty-two inbound and outbound doorbells  
• Four inbound and outbound message registers  
• Two shared scratchpad registers  
Allows up to sixteen masters to communicate through the non-  
transparent port  
No limit on the number of supported outstanding transactions  
through the non-transparent bridge  
Completely symmetric non-transparent bridge operation  
allows similar/same configuration software to be run  
Supports direct connection to a transparent or non-transparent  
port of another switch  
Features  
◆
High Performance PCI Express Switch  
–
–
–
–
–
–
–
–
–
–
Twelve PCI Express lanes (2.5Gbps), three switch ports  
Delivers 48 Gbps (6 GBps) of aggregate switching capacity  
Low latency cut-through switch architecture  
Support for Max Payload size up to 2048 bytes  
Supports one virtual channel and eight traffic classes  
PCI Express Base specification Revision 1.0a compliant  
Block Diagram  
3-Port Switch Core  
Port  
Arbitration  
Frame Buffer  
Route Table  
Scheduler  
Transaction Layer  
Transaction Layer  
Data Link Layer  
Transaction Layer  
Data Link Layer  
Non-  
Transparent  
Bridge  
Data Link Layer  
Multiplexer / Demultiplexer  
Multiplexer / Demultiplexer  
Multiplexer / Demultiplexer  
Phy  
Logical  
Phy  
Logical  
Phy  
Logical  
Phy  
Logical  
Phy  
Logical  
Phy  
Logical  
Phy  
Logical  
Phy  
Logical  
Phy  
Logical  
Layer  
Layer  
Layer  
Layer  
Layer  
Layer  
Layer  
Layer  
Layer  
...  
...  
...  
SerDes SerDes  
SerDes  
SerDes SerDes  
SerDes  
SerDes SerDes  
SerDes  
12 PCI Express Lanes  
x4 Upstream Port and Two x4 Downstream Ports  
Figure 1 Internal Block Diagram  
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.Inc.  
1 of 29  
April 11, 2007  
DSC 6929  
© 2007 Integrated Device Technology, Inc.  
*Notice: The information in this document is subject to change without notice  
1234567...29

中文翻译

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