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89HPES12T3G2

更新时间: 2024-02-10 09:18:43
品牌 Logo 应用领域
艾迪悌 - IDT 开关PC
页数 文件大小 规格书
31页 563K
描述
12-Lane 3-Port Gen2 PCI Express Switch

89HPES12T3G2 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:CABGA
包装说明:19 X 19 MM, 1 MM PITCH, MS-034/AAAG-1, CABGA-324针数:324
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.1
地址总线宽度:总线兼容性:PCI
最大时钟频率:125 MHz驱动器接口标准:IEEE 1149.1
外部数据总线宽度:JESD-30 代码:S-PBGA-B324
JESD-609代码:e0长度:19 mm
湿度敏感等级:3端子数量:324
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA324,18X18,40封装形状:SQUARE
封装形式:GRID ARRAY峰值回流温度(摄氏度):225
电源:1,2.5,3.3 V认证状态:Not Qualified
座面最大高度:1.72 mm子类别:Bus Controllers
最大供电电压:1.1 V最小供电电压:0.9 V
标称供电电压:1 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn63Pb37)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:19 mm
uPs/uCs/外围集成电路类型:BUS CONTROLLER, PCIBase Number Matches:1

89HPES12T3G2 数据手册

 浏览型号89HPES12T3G2的Datasheet PDF文件第2页浏览型号89HPES12T3G2的Datasheet PDF文件第3页浏览型号89HPES12T3G2的Datasheet PDF文件第4页浏览型号89HPES12T3G2的Datasheet PDF文件第5页浏览型号89HPES12T3G2的Datasheet PDF文件第6页浏览型号89HPES12T3G2的Datasheet PDF文件第7页 
89HPES12T3G2  
Data Sheet  
Advance Information*  
12-Lane 3-Port  
Gen2 PCI Express® Switch  
®
Legacy Support  
Device Overview  
PCI compatible INTx emulation  
Bus locking  
The 89HPES12T3G2 is a member of IDT’s PRECISE™ family of PCI  
Express® switching solutions. The PES12T3G2 is a 12-lane, 3-port  
Gen2 peripheral chip that performs PCI Express Base switching with a  
feature set optimized for high performance applications such as servers,  
storage, and communications/networking. It provides connectivity and  
switching functions between a PCI Express upstream port and two  
downstream ports and supports switching between downstream ports.  
Highly Integrated Solution  
Incorporates on-chip internal memory for packet buffering and  
queueing  
Integrates twelve 5 Gbps embedded SerDes with 8b/10b  
encoder/decoder (no separate transceivers needed)  
• Receive equalization (RxEQ)  
Reliability, Availability, and Serviceability (RAS) Features  
Features  
High Performance PCI Express Switch  
Internal end-to-end parity protection on all TLPs ensures data  
integrity even in systems that do not implement end-to-end  
CRC (ECRC)  
Supports ECRC and Advanced Error Reporting  
Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O  
Compatible with Hot-Plug I/O expanders used on PC mother-  
boards  
Supports Hot-Swap  
Twelve 5 Gbps Gen2 PCI Express lanes  
Three switch ports  
• One x4 upstream port  
• Two x4 downstream ports  
Low latency cut-through switch architecture  
Support for Max Payload Size up to 2048 bytes  
One virtual channel  
Eight traffic classes  
PCI Express Base Specification Revision 2.0 compliant  
Power Management  
Utilizes advanced low-power design techniques to achieve low  
typical power consumption  
Flexible Architecture with Numerous Configuration Options  
Automatic per port link width negotiation to x4, x2 or x1  
Automatic lane reversal on all ports  
Automatic polarity inversion  
Support PCI Express Power Management Interface specifica-  
tion (PCI-PM 2.0)  
Ability to load device configuration from serial EEPROM  
Block Diagram  
3-Port Switch Core / 12 PCI Express Lanes  
Port  
Frame Buffer  
Route Table  
Arbitration  
Scheduler  
Transaction Layer  
Transaction Layer  
Data Link Layer  
Transaction Layer  
Data Link Layer  
Data Link Layer  
Multiplexer / Demultiplexer  
Multiplexer / Demultiplexer  
Multiplexer / Demultiplexer  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
SerDes  
SerDes  
SerDes  
(Port 2)  
(Port 0)  
(Port 4)  
Figure 1 Internal Block Diagram  
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.  
1 of 31  
September 4, 2007  
DSC 6930  
© 2007 Integrated Device Technology, Inc.  
*Notice: The information in this document is subject to change without notice  

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