Datasheet > 879893AYILFT

879893AYILFT

更新时间： 2024-01-31 05:42:40

品牌	Logo	应用领域
艾迪悌 - IDT		DCS 分布式控制系统
页数	文件大小	规格书
16页	205K
描述
Low Skew, 1-to-12 (IDCS) LVCMOS/LVTTL Clock Generator

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879893AYILFT 数据手册

879893 Datasheet

Table 1. Pin Descriptions

Number

Name

Type

Description

1, 12, 16,

20, 29, 32,

37, 41, 45

GND

Power

Power supply ground.

QFB

Output

Input

Clock feedback output. LVCMOS / LVTTL interface levels.

Pulldown Feedback control input. LVCMOS / LVTTL interface levels.

Manual alarm input. Selects automatic switch mode or manual reference

clock. Clock failure detection, and nALARM_RST and CLK_IND output

flags are enabled. When LOW, IDCS is disabled. When HIGH, IDCS is

enabled. IDCS overrides REF_SEL on a clock failure. IDCS operation

requires nPLL_EN = 0. LVCMOS / LVTTL interface levels.

nMAN/A

Input

Pullup

5, 13, 17,

21, 25, 36,

40, 44, 48

V_DD

Power

Core supply pins.

6, 7

CLK0, CLK1

V_DDA

Input

Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels.

Analog supply pin.

Power

When LOW, indicates clock failure on CLK0.

LVCMOS / LVTTL interface levels.

nALARM0

nALARM1

Output

When LOW, indicates clock failure on CLK1.

LVCMOS / LVTTL interface levels.

Indicates currently selected input reference clock. When LOW, CLK0 is the

reference clock. When HIGH, CLK1 is the reference clock.

LVCMOS / LVTTL interface levels.

CLK_IND

Output

14, 15, 18,

19, 22, 23

QB5, QB4, QB3,

QB2, QB1, QB0

Single-ended Bank B clock outputs. LVCMOS/LVTTL interface levels.

Active High Master Reset. Active Low Output Enable. When logic LOW,

the internal dividers and the outputs are enabled. When logic HIGH, the

internal dividers are reset and the outputs are in a high-impedance state.

nOE/MR

Input

Pulldown

LVCMOS / LVTTL interface levels.

27, 28,

30, 31

FSEL3, FSEL2,

FSEL1, FSEL0

Clock frequency selection and configuration of clock divider modes.

LVCMOS / LVTTL interface levels.

Input

Pulldown

Selects PLL or static test mode. When LOW, PLL is enabled. When HIGH,

Pulldown PLL is bypassed and IDCS is disabled. The VCO output is replaced by the

reference clock signal fREF. LVCMOS / LVTTL interface levels.

nPLL_EN

Selects the primary reference clock. When LOW, selects CLK0 as the

Pulldown primary clock source. When HIGH, selects CLK1 as the primary clock

source. LVCMOS / LVTTL interface levels.

REF_SEL

Input

Resets the alarm flags and selected reference clock.

nALARM_RST

Input

Pullup

LVCMOS / LVTTL interface levels.

38, 39 42,

43, 46, 47

QA0, QA1, QA2,

QA3, QA4, QA5

Output

Single-ended Bank A clock outputs. LVCMOS/LVTTL interface levels.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Revision B, January 10, 2017

1 234 5 6 7...16

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879893AYILFT 替代型号

型号	品牌	替代类型	描述	数据表
879893AYILF	IDT	完全替代	Low Skew, 1-to-12 (IDCS) LVCMOS/LVTTL Clock Generator

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