Datasheet > 879893AYILFT

879893AYILFT

更新时间： 2024-01-14 06:42:22

品牌	Logo	应用领域
艾迪悌 - IDT		DCS 分布式控制系统
页数	文件大小	规格书
16页	205K
描述
Low Skew, 1-to-12 (IDCS) LVCMOS/LVTTL Clock Generator

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879893AYILFT 数据手册

879893 Datasheet

AC Electrical Characteristics

Table 5A. AC Characteristics, V_DD= 3.3V ± 5%, T_A= -40°C to 85°C

Parameter Symbol

Test Conditions

Minimum

7.5

Typical Maximum

Units

MHz

f_OUT

f_REF

Output Frequency

200

100

Input Frequency

PLL Closed Loop Bandwidth

0.8 to 4

V_DD= 3.3V±5%; FSEL = 111x

V_DD= 3.3V±5%

-35

120

130

Propagation Delay, (Static Phase

Offset, CLKx to FB); NOTE 1, 2, 3

t(Ø)

within bank

Output Skew;

bank-to-bank

NOTE 1, 2, 3, 4

tsk(o)

135

315

any output to QFB

ps/

cycle

f_REF= 62.5MHz, FSEL = 1000

FSEL = XXX0

160

280

425

ps/

cycle

t

Rate of Period Change; NOTE 2

100

200

ps/

cycle

FSEL = XXX1

FSEL3 = 0

FSEL3 = 1

150

190

700

tjit(cc)

Cycle-to-Cycle Jitter; NOTE 2, 3

Output Clock Period Deviation when

switching from primary input to

secondary; NOTE 2

f_REF= 62.5MHz, FSEL = 1000

-600

-800

t_CYCLE

tjit(per)

800

FSEL3 = 0

150

Period Jitter; NOTE 2, 3

FSEL3 = 1, measured on QBx

FB = 4;

FSEL [0:2] = 100 or 111 (1)

FB = 6;

FSEL [0:2] = 010 (1)

tjit(Ø)

I/O Phase Jitter, (1); NOTE 2, 3

FB = 8; FSEL [0:2] = 001, 011

or 110 (1)

FB = 16;

FSEL [0:2] = 000 or 101 (1)

t_R/ t_F

t_PZL, t_PZH

t_PLZ, t_PHZ

t_L

Output Rise/Fall Time

20% to 80%

250

600

Output Enable Time; NOTE 2

Output Disable Time; NOTE 2

PLL Lock Time; NOTE 2

Output Duty Cycle

odc

All parameters measured at f_MAXunless noted otherwise.

NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal, when the PLL is locked and

the input reference frequency is stable.

NOTE 2: These parameters are guaranteed by characterization. Not tested in production.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V_DD/2.

Revision B, January 10, 2017

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879893AYILFT 替代型号

型号	品牌	替代类型	描述	数据表
879893AYILF	IDT	完全替代	Low Skew, 1-to-12 (IDCS) LVCMOS/LVTTL Clock Generator

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