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874328BYI-01LFT PDF预览

874328BYI-01LFT

更新时间: 2024-10-30 01:13:35
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
23页 370K
描述
2.5V Differential Clock Divider/Buffer

874328BYI-01LFT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Lifetime Buy零件包装代码:TQFP
包装说明:10 X 10 MM, 1 MM HEIGHT, ROHS COMPLIANT, MS-026ACD, TQFP-64针数:64
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.46
系列:5V输入调节:STANDARD
JESD-30 代码:S-PQFP-G64JESD-609代码:e3
长度:10 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:6端子数量:64
实输出次数:6最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TFQFP封装等效代码:TQFP64,.47SQ
封装形状:SQUARE封装形式:FLATPACK
峰值回流温度(摄氏度):260电源:2.5 V
Prop。Delay @ Nom-Sup:4.8 ns传播延迟(tpd):4.8 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.07 ns
座面最大高度:1.2 mm子类别:Clock Drivers
最大供电电压 (Vsup):2.625 V最小供电电压 (Vsup):2.375 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:10 mm最小 fmax:650 MHz
Base Number Matches:1

874328BYI-01LFT 数据手册

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2.5V Differential Clock Divider/Buffer  
874328I-01  
Data Sheet  
General Description  
Features  
One differential input LVPECL reference clock  
The 874328I-01 is a high-performance differential ÷1 and ÷4 clock  
divider and fanout buffer. The device is designed for the  
Differential pair can accept the following differential input  
levels: LVPECL, LVDS, CML, SSTL  
frequency-division and signal fanout of high-frequency, low  
phase-noise clock signals. The differential input signal is frequency  
divided by ÷1 and ÷4. Three LVPECL and three LVDS output banks  
are provided with a total of twenty differential outputs. The  
874328I-01 is characterized to operate from a 2.5V power supply.  
Guaranteed output-to-output and part-to-part skew characteristics  
make the 874328I-01 ideal for those clock distribution applications  
demanding well-defined performance and repeatability.  
Integrated input termination resistors  
One bank of three LVPECL outputs (÷1 frequency-divided)  
One bank of three LVPECL outputs (÷4 frequency-divided)  
One bank of two LVPECL outputs (÷4 frequency-divided)  
Two banks of three LVDS outputs (÷4 frequency-divided)  
One bank of six LVDS outputs (÷4 frequency-divided)  
Total of twenty differential clock outputs  
Maximum input frequency: 650MHz  
Maximum output frequency: 650MHz (÷1 outputs)  
Maximum output frequency: 162.5MHz (÷4 outputs)  
LVCMOS interface levels for all control inputs  
Output skew: 70ps (maximum)  
Pin Assignment  
Part-to-part skew: 250ps (maximum)  
Full 2.5V supply voltage  
Available in lead-free (RoHS 6) package  
-40°C to 85°C ambient operating temperature  
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49  
VEE  
VCCOA  
1
2
3
4
5
OEF  
VCCOC  
nQC1  
QC1  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
QA0  
nQA0  
QA1  
ICS874328I-01  
64-Lead TQFP, E-Pad  
10mm x 10mm x 1.0mm  
package body  
nQC0  
QC0  
OEE  
OED  
VCC  
nQA1  
QA2  
nQA2  
6
7
8
9
QB0  
nQB0  
QB1  
Y package  
Top View  
OEC  
nCLK  
10  
11  
12  
13  
14  
nQB1  
VREF  
VT  
CLK  
37  
Block Diagram  
QB2  
nQB2  
36  
35  
VCCOB  
15  
16  
OEB  
OEA  
34  
33  
QA[0:2]  
nQA[0:2]  
CLK_EN  
÷1  
÷4  
17 18 19 20 21  
23 24 25 26 27 28 29 30 31 32  
22  
fREF  
CLK  
(LVPECL)  
nCLK  
50  
50  
QB[0:2]  
nQB[0:2]  
(LVPECL)  
Pullup  
VT  
VREF  
Pullup  
Pullup  
Pullup  
Pullup  
Pullup  
Pullup  
QC[0:1]  
nQC[0:1]  
CLK_EN  
(LVPECL)  
QD[0:2]  
nQD[0:2]  
(LVDS)  
©2016 Integrated Device Technology, Inc  
1
Revision A January 27, 2016  

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