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8735AMI-21T PDF预览

8735AMI-21T

更新时间： 2024-02-14 18:34:02
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
16页 146K
描述
PLL Based Clock Driver, 8735 Series, 1 True Output(s), 0 Inverted Output(s), PDSO20, 7.50 MM X 12.80 MM, 2.30 MM HEIGHT, MS-013, MO-119, SOIC-20

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8735AMI-21T 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：7.50 MM X 12.80 MM, 2.30 MM HEIGHT, MS-013, MO-119, SOIC-20针数：20
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.81
Is Samacsys：N系列：8735
输入调节：DIFFERENTIALJESD-30 代码：R-PDSO-G20
JESD-609代码：e0长度：12.8 mm
逻辑集成电路类型：PLL BASED CLOCK DRIVER湿度敏感等级：1
功能数量：1反相输出次数：
端子数量：20实输出次数：1
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP20,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：225
电源：3.3 VProp。Delay @ Nom-Sup：4.9 ns
传播延迟（tpd）：4.9 ns认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.035 ns座面最大高度：2.65 mm
子类别：Clock Drivers最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn85Pb15)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：7.5 mm
最小 fmax：700 MHzBase Number Matches：1

8735AMI-21T 数据手册

 浏览型号8735AMI-21T的Datasheet PDF文件第6页浏览型号8735AMI-21T的Datasheet PDF文件第7页浏览型号8735AMI-21T的Datasheet PDF文件第8页浏览型号8735AMI-21T的Datasheet PDF文件第10页浏览型号8735AMI-21T的Datasheet PDF文件第11页浏览型号8735AMI-21T的Datasheet PDF文件第12页 
ICS8735I-21  
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL  
ZERO DELAY CLOCK GENERATOR  
TERMINATION FOR LVPECL OUTPUTS  
The clock layout topology shown below is a typical termi-  
nation for LVPECL outputs. The two different layouts men-  
tioned are recommended only as guidelines.  
ance techniques should be used to maximize operating  
frequency and minimize signal distortion. Figures 4A and  
4B show two different layouts which are recommended only  
as guidelines. Other suitable clock layouts may exist and it  
would be recommended that the board designers simulate  
to guarantee compatibility across all printed circuit and clock  
component process variations.  
FOUT and nFOUT are low impedance follower outputs that  
generate ECL/LVPECL compatible outputs. Therefore, ter-  
minating resistors (DC current path to ground) or current  
sources must be used for functionality. These outputs are  
designed to drive 50Ω transmission lines. Matched imped-  
3.3V  
Zo = 50Ω  
125Ω  
125Ω  
FOUT  
FIN  
Zo = 50Ω  
Zo = 50Ω  
Z
o = 50Ω  
FOUT  
FIN  
50Ω  
50Ω  
VCC - 2V  
1
RTT =  
Zo  
RTT  
((VOH + VOL) / (VCC – 2)) – 2  
84Ω  
84Ω  
FIGURE 4A. LVPECL OUTPUTT ERMINATION  
FIGURE 4B. LVPECL OUTPUTT ERMINATION  
SCHEMATIC EXAMPLE  
follows: SEL [3:0] = 0101; PLL_SEL = 1  
The decoupling capacitors should be physically located near  
the power pin.  
Figure 5 shows a schematic example of the ICS8735I-21. In  
this example, the input is driven by an HCSL driver. The zero  
delay buffer is configured to operate at 155.52MHz input and  
77.75MHz output. The logic control pins are configured as  
3.3V  
R7  
VCC  
VCCA  
U1  
Zo = 50 Ohm  
10  
(155.5 MHz)  
1
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
C11  
0.01u  
CLK  
2
nc  
SEL1  
SEL0  
VCCI  
PLL_SEL  
VCCA  
SEL3  
VCCO  
Q
SEL1  
SEL0  
VCC  
PLL_SEL  
VCCA  
SEL3  
C16  
10u  
nCLK  
3
4
5
6
7
8
9
10  
MR  
VCC  
Zo = 50 Ohm  
VCCI  
nFB_IN  
FB_IN  
SEL2  
VEE  
QFB  
nQFB  
SEL2  
HCSL  
VCC  
Zo = 50 Ohm  
Zo = 50 Ohm  
R8  
50  
R9  
50  
+
nQ  
VCC  
R1  
50  
R2  
50  
ICS8735-21  
-
LVPECL_input  
(77.75 MHz)  
RU3  
1K  
RU4  
1K  
RU5  
SP  
RU6  
1K  
RU7  
SP  
R4  
50  
R5  
50  
R3  
50  
PLL_SEL  
SEL0  
SEL1  
SEL2  
SEL3  
Bypass capacitors located  
near the power pins  
R6  
50  
VCC  
(U1-4)  
(U1-17)  
(U1-13)  
VCC=3.3V  
RD3  
SP  
RD4  
SP  
RD5  
1K  
RD6  
SP  
RD7  
1K  
C1  
0.1uF  
C2  
0.1uF  
C3  
0.1uF  
SEL[3:0] = 0101,  
Divide by 2  
SP = Space (i.e. not intstalled)  
FIGURE 5. ICS8735I-21 LVPECL BUFFER SCHEMATIC EXAMPLE  
www.idt.com  
8735AMI-21  
REV. D OCTOBER 22, 2013  
9
1...6789101112...16

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