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8735AYI-01T PDF预览

8735AYI-01T

更新时间: 2024-09-29 20:55:43
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
18页 263K
描述
PLL Based Clock Driver, 8735 Series, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBA, LQFP-32

8735AYI-01T 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP, QFP32,.35SQ,32针数:32
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.81
系列:8735输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQFP-G32JESD-609代码:e0
长度:7 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:32
实输出次数:5最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP32,.35SQ,32
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):240电源:3.3 V
Prop。Delay @ Nom-Sup:4.9 ns传播延迟(tpd):4.9 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.055 ns
座面最大高度:1.6 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:7 mm最小 fmax:700 MHz
Base Number Matches:1

8735AYI-01T 数据手册

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ICS8735I-01  
1:5 DIFFERENTIAL-TO-3.3V LVPECL  
ZERO DELAY CLOCK GENERATOR  
NRND  
Not Recommended for New Designs 10/22/13  
For replacement device use ICS8735BYI-01LF or ICS8735BKI-01LF  
GENERAL DESCRIPTION  
FEATURES  
The ICS8735I-01 is a highly versatile 1:5 Differential-to- Five differential 3.3V LVPECL outputs  
3.3V LVPECL clock generator . The ICS8735I-01 has a fully  
integrated PLL and can be configured as zero delay buffer,  
Selectable differential clock inputs  
multiplier or divider, and has an output frequency range of  
31.25MHz to 700MHz. The reference divider, feedback  
divider and output divider are each programmable, thereby  
allowing for the following output-to-input frequency ratios:  
8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8.The external feedback allows  
the device to achieve “zero delay” between the input clock  
and the output clocks. The PLL_SEL pin can be used to  
bypass the PLL for system test and debug purposes. In  
bypass mode, the reference clock is routed around the PLL  
and into the internal output dividers.  
CLKx, nCLKx pair can accept the following differential  
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL  
Output frequency range: 31.25MHz to 700MHz  
Input frequency range: 31.25MHz to 700MHz  
VCO range: 250MHz to 700MHz  
Programmable dividers allow for the following output-to-input  
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8  
External feedback for “zero delay” clock regeneration  
with configurable frequencies  
Cycle-to-cycle jitter: 40ps (maximum)  
Output skew: 55ps (maximum)  
Static phase offset: 50ps 100ps  
3.3V supply voltage  
-40°C to 85°C ambient operating temperature  
Available in both standard (RoHS 5) and lead-free  
(RoHS 6) packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
Q0  
nQ0  
PLL_SEL  
Q1  
nQ1  
÷1, ÷2, ÷4, ÷8,  
0
÷16, ÷32, ÷64  
CLK0  
nCLK0  
32 31 30 29 28 27 26 25  
Q2  
nQ2  
0
SEL0  
SEL1  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
V
CCO  
1
CLK1  
1
Q3  
Q3  
nQ3  
nCLK1  
CLK0  
nQ3  
Q2  
PLL  
Q4  
nQ4  
nCLK0  
CLK1  
CLK_SEL  
ICS8735I-01  
nQ2  
Q1  
8:1, 4:1, 2:1, 1:1,  
1:2, 1:4, 1:8  
nCLK1  
CLK_SEL  
FB_IN  
nFB_IN  
nQ1  
MR  
VCCO  
9
10 11 12 13 14 15 16  
SEL0  
SEL1  
SEL2  
SEL3  
MR  
32-Lead LQFP  
7mm x 7mm x 1.4mm package body  
Y Package  
TopView  
32-LeadVFQFN  
5mm x 5mm x 0.95 package body  
K Package  
TopView  
8735AYI-01  
www.idt.com  
REV. D OCTOBER 22, 2013  
1

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