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87339AM-01LF PDF预览

87339AM-01LF

更新时间: 2024-11-30 19:59:47
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
16页 214K
描述
Low Skew Clock Driver, 87339 Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 7.50 X 12.80 MM, 2.25 MM HEIGHT, ROHS COMPLIANT, MS-013, MO-119, SOIC-20

87339AM-01LF 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:SOIC包装说明:SOP, SOP20,.4
针数:20Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.18其他特性:ECL MODE: VEE=-3 TO -3.6V AT VCC=0V
系列:87339输入调节:DIFFERENTIAL LATCHED
JESD-30 代码:R-PDSO-G20JESD-609代码:e3
长度:12.8 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:20
实输出次数:4最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:2.1 ns传播延迟(tpd):2.1 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.035 ns
座面最大高度:2.65 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:7.5 mmBase Number Matches:1

87339AM-01LF 数据手册

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ICS87339-01  
LOW SKEW, ÷2/4,÷4/6,  
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR  
GENERAL DESCRIPTION  
FEATURES  
The ICS87339-01 is a low skew, high performance Two divide by 2/4 differential 3.3V LVPECL outputs;  
Differential-to-3.3V LVPECL / ECL Clock Generator/Divider.  
The ICS87339-01 has one differential clock input pair. The  
CLK, nCLK pair can accept most standard differential input  
levels. The clock enable isinternally synchronized to  
eliminate runt pulses on theoutputs during asynchronous  
assertion/deassertion of the clock enable pin.  
two divide by 4/6 differential 3.3V LVPECL outputs  
One differential CLK, nCLK input pair  
CLK, nCLK pair can accept the following differential  
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL  
Maximum input frequency: 1GHz  
Guaranteed output and part-to-part skew characteristics  
make the ICS87339-01 ideal for clock distribution applications  
demanding well defined performance and repeatability.  
Translates any single ended input signal (LVCMOS, LVTTL,  
GTL) to LVPECL levels with resistor bias on nCLK input  
Output skew: 35ps (maximum)  
Part-to-part skew: 385ps (maximum)  
Bank skew: Bank A - 30ps (maximum)  
Bank B - 25ps (maximum)  
Propagation delay: 2.1ns (maximum)  
LVPECL mode operating voltage supply range:  
VCC = 3V to 3.6V, VEE = 0V  
ECL mode operating voltage supply range:  
VCC = 0V, VEE = -3.6V to -3V  
0°C to 70°C ambient operating temperature  
Industrial temperature information available upon request  
Available in both standard and lead-free RoHS compliant  
packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
DIV_SELA  
VCC  
nCLK_EN  
DIV_SELB  
CLK  
nCLK  
RESERVED  
MR  
VCC  
nc  
DIV_SELA  
VCC  
1
2
3
4
5
6
7
8
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
QA0  
nQA0  
QA0  
nQA0  
QA1  
nQA1  
QB0  
nQB0  
QB1  
nQB1  
VEE  
D
nCLK_EN  
÷2, ÷4  
R
QA1  
nQA1  
Q
LE  
CLK  
nCLK  
9
10  
QB0  
nQB0  
ICS87339-01  
20-Lead SOIC, M Package  
7.5mm x 12.8mm x 2.25  
package body  
÷4, ÷6  
QB1  
nQB1  
R
MR  
Top View  
DIV_SELB  
87339AM-01  
www.idt.com  
REV. B AUGUST 2, 2010  
1

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