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8733BY-01T PDF预览

8733BY-01T

更新时间: 2024-11-30 20:52:03
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
18页 205K
描述
Clock Driver

8733BY-01T 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:not_compliant风险等级:5.92
JESD-609代码:e0湿度敏感等级:3
端子面层:Tin/Lead (Sn85Pb15)Base Number Matches:1

8733BY-01T 数据手册

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PRELIMINARY  
ICS8733-01  
Integrated  
Circuit  
Systems, Inc.  
700MHZ FORWARD ERROR CORRECTION  
DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR  
GENERAL DESCRIPTION  
FEATURES  
Clock synthesis of 14/15 or 15/14 of the input reference  
clock to be utilized in Forward Error Correction (FEC)  
applications  
The ICS8733-01 is a dual output, Differential-  
to-3.3V LVPECL Clock Generator and a  
member of the HiPerClockSfamily of High  
Performance Clock Solutions from ICS. The  
ICS8733-01 is designed to be used for applica-  
HiPerClockS™  
Fully integrated PLL  
2 differential 3.3V LVPECLoutputs  
1 differential clock input pair  
tions utilizing Forward Error Correction (FEC) designs. The  
ICS8733-01 generates a 14/15 or a 15/14 output clock based  
upon the input reference clock in order to incorporate the  
FEC capability required by the application.  
CLK, nCLK pair can accept the following differential input  
levels: LVPECL, LVHSTL, LVDS, SSTL, HCSL  
Clock generation is performed by a fully integrated and  
low-jitter phase-locked loop. The ICS8733-01 accepts any  
differential signal as its input with an input reference fre-  
quency range of 36.27MHz to 750MHz. There are two  
LVPECL outputs which can generate output frequencies of  
38.88MHz to 700MHz.  
Output frequency range: 38.88MHz - 700MHz  
Input frequency range: 36.27MHz - 750MHz  
VCO range: 200MHz to 700MHz  
PLL bypass and test modes that support in-circuit testing  
and on-chip functional block characterization  
Cycle-to-cycle jitter: 20ps (typical)  
Period jitter: TBD  
Output skew: 10ps (maximum)  
3.3V supply voltage  
0°C to 70°C ambient operating temperature  
BLOCK DIAGRAM  
DIV_SEL0  
DIV_SEL1  
MR  
PIN ASSIGNMENT  
32 31 30 29 28 27 26 25  
PLL_SEL  
nc  
FEC_NSEL  
FEC_MSEL  
VEE  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
CLK  
N ”  
n_CLK  
VCCA  
CLK  
÷14  
0
nCLK  
VCCA  
ICS8733-01  
1
÷15  
VEE  
DIV_SEL0  
DIV_SEL1  
nc  
TEST_SEL  
TEST_EN  
VEE  
FEC_NSEL  
MR  
9
10 11 12 13 14 15 16  
0 0  
0 1  
1 0  
1 1  
÷¼  
÷1  
÷2  
÷4  
0
1
FOUT1  
nFOUT1  
PLL  
FOUT0  
nFOUT0  
32-Lead LQFP  
÷15  
0
1
7mm x 7mm x 1.4mm package body  
0
1
Y Package  
Top View  
TEST  
÷14  
M ”  
FEC_MSEL  
TEST_SEL  
TEST_EN  
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial  
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.  
8733BY-01  
www.icst.com/products/hipercocks.html  
REV. A JANUARY 17, 2002  
1

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