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8732AY-11T PDF预览

8732AY-11T

更新时间： 2024-11-28 19:57:07
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
15页 283K
描述
Clock Driver

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中文翻译

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8732AY-11T 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
Reach Compliance Code：unknown风险等级：5.92
Base Number Matches：1

8732AY-11T 数据手册

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PRELIMINARY  
ICS8732-11  
Integrated  
Circuit  
Systems, Inc.  
LOW  
V
OLTAGE, LOW  
S
KEW  
3.3V LVPECL CLOCK  
GENERATOR  
GENERAL DESCRIPTION  
Features  
• 10 differential 3.3V LVPECL outputs  
The ICS8732-11 is a low voltage, low skew,  
ICS  
3.3V LVPECL Clock Generator and a member of  
the HiPerClockS™ family of High Performance  
Clock Solutions from ICS. The ICS8732-11 has  
two selectable clock inputs. The CLK0, nCLK0  
• Selectable differential CLK0, nCLK0 or  
LVCMOS/LVTTL CLK1 inputs  
HiPerClockS™  
• CLK0, nCLK0 supports the following input types:  
LVPECL, LVDS, LVHSTL, SSTL, HCSL  
pair can accept most standard differential input levels.  
The single ended clock input accepts LVCMOS or LVTTL  
input levels.The ICS8732-11 has a fully integrated PLL along  
with frequency configurable outputs. An external feedback  
input and outputs regenerate clocks with “zero delay”.  
• CLK1 accepts the following input levels:  
LVCMOS or LVTTL  
• Maximum output frequency: 700MHz  
• VCO range: 250MHz to 700MHz  
The ICS8732-11 has multiple divide select pins for each bank  
of outputs along with 3 independent feedback divide select  
pins allowing the ICS8732-11 to function both as a frequency  
multiplier and divider. The PLL_SEL input can be used  
to bypass the PLL for test and system debug purposes.  
In bypass mode, the input clock is routed around the PLL  
and into the internal output dividers.  
• External feedback for “zero delay” clock regeneration  
with configurable frequencies  
• Cycle-to-cycle jitter: CLK, nCLK -TBD  
CLK1 - TBD  
• Output skew: TBD  
• Static phase offset: TBD  
• Industrial temperature information available upon request  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
CLK_SEL  
CLK0  
0
QA0  
nCLK0  
CLK1  
0
1
÷1 ÷2 ÷4 ÷6  
÷1 ÷2 ÷4 ÷8  
nQA0  
52 51 50 49 48 47 46 45 44 43 42 41 40  
1
PLL  
VCCO  
QA0  
1
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
VCCO  
nQB3  
QB3  
nQB2  
QB2  
VEE  
QA1  
nQA1  
2
FB_IN  
÷4 ÷6 ÷8 ÷10  
nFB_IN  
÷8 ÷12 ÷16 ÷20  
nQA0  
QA1  
QA2  
nQA2  
3
4
QA3  
nQA3  
nQA1  
VEE  
5
PLL_SEL  
6
PLL_SEL  
VCCO  
QA2  
7
QB0  
MR  
ICS8732-11  
DIV_SELA0  
DIV_SELA1  
DIV_SELB0  
DIV_SELB1  
FBDIV_SEL0  
FBDIV_SEL1  
FBDIV_SEL2  
nQB0  
8
VCCO  
nQB1  
QB1  
nQB0  
QB0  
VEE  
QB1  
nQB1  
9
nQA2  
QA3  
10  
11  
12  
13  
QB2  
nQB2  
nQA3  
VEE  
QB3  
nQB3  
14 15 16 17 18 19 20 21 22 23 24 25 26  
QFB0  
nQFB0  
QFB1  
nQFB1  
52-Lead LQFP  
10mm x 10mm x 1.4mm package body  
Y package  
MR  
TopView  
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial  
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.  
8732AY-11  
www.icst.com/products/hiperclocks.html  
REV. A MARCH 3, 2004  
1
1234567...15

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