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858011AKLFT PDF预览

858011AKLFT

更新时间: 2024-11-07 20:36:55
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
12页 187K
描述
Clock Driver, 858011 Series, 2 True Output(s), 0 Inverted Output(s), 3 X 3 MM, 0.95 MM HEIGHT, ROHS COMPLIANT, MO-220, VFQFN-16

858011AKLFT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFN
包装说明:HVQCCN, LCC16,.12SQ,20针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.84系列:858011
输入调节:DIFFERENTIALJESD-30 代码:S-XQCC-N16
JESD-609代码:e3长度:3 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER功能数量:1
反相输出次数:端子数量:16
实输出次数:2最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装等效代码:LCC16,.12SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260电源:2.5/3.3 V
认证状态:Not Qualified座面最大高度:1 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.63 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:3 mm
Base Number Matches:1

858011AKLFT 数据手册

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PRELIMINARY  
ICS858011  
Integrated  
Circuit  
Systems, Inc.  
LOW SKEW, 1-TO-2  
DIFFERENTIAL-TO-CML FANOUT BUFFER  
GENERAL DESCRIPTION  
FEATURES  
The ICS858011 is a high speed 1-to-2 Differential- Two differential CML outputs  
ICS  
HiPerClockS™  
to-CML Fanout Buffer and is a member of the  
One differential LVPECL clock input  
HiPerClockS™family of high performance clock  
solutions from ICS.The ICS858011 is optimized  
for high speed and very low output skew, making  
IN, nIN pair can accept the following differential input  
levels: LVPECL, LVDS, CML, SSTL  
it suitable for use in demanding applications such as SONET,  
1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The  
internally terminated differential input and VREF_AC pin allow  
other differential signal families such as LVDS, LVHSTL and  
CML to be easily interfaced to the input with minimal use of  
external components.The ICS858011 is packaged in a small  
3mm x 3mm 16-pin VFQFN package which makes it ideal  
for use in space-constrained applications.  
Output frequency: > 2.5GHz (typical)  
Output skew: TBD  
Part-to-part skew: TBD  
Additive phase jitter, RMS: <100fs (design target)  
Propagation delay: 388ps (typical)  
Operating voltage supply range:  
VCC = 2.375V to 3.63V, VEE = 0V  
-40°C to 85°C ambient operating temperature  
Available in both standard and lead-free RoHS compliant  
packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
16 15 14 13  
IN  
VT  
1
2
3
4
12 Q0  
11 nQ0  
10 nQ1  
VREF_AC  
Q0  
nQ0  
IN  
VT  
nIN  
9
Q1  
5
6
7
8
nIN  
Q1  
nQ1  
VREF_AC  
ICS858011  
16-LeadVFQFN  
3mm x 3mm x 0.95 package body  
K Package  
TopView  
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial  
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.  
858011AK  
www.icst.com/products/hiperclocks.html  
REV. A JANUARY 19, 2006  
1

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