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854S204BGILFT PDF预览

854S204BGILFT

更新时间： 2024-02-26 17:08:37
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
23页 1425K
描述
Low Skew, Dual, Programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer

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854S204BGILFT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP16,.25针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.8
系列：854输入调节：DIFFERENTIAL
JESD-30 代码：R-PDSO-G16JESD-609代码：e3
长度：5 mm逻辑集成电路类型：LOW SKEW CLOCK DRIVER
湿度敏感等级：1功能数量：2
反相输出次数：端子数量：16
实输出次数：2最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP16,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：2.5/3.3 V
Prop。Delay @ Nom-Sup：0.5 ns传播延迟（tpd）：0.5 ns
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.015 ns
座面最大高度：1.2 mm子类别：Clock Drivers
最大供电电压 (Vsup)：2.625 V最小供电电压 (Vsup)：2.375 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn) - annealed
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：4.4 mmBase Number Matches：1

854S204BGILFT 数据手册

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ICS854S204I Data Sheet  
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER  
AC Electrical Characteristics  
Table 5A. LVDS AC Characteristics, VDD = 3.3V 5%, TA = -40°C to 85°C  
Symbol  
fMAX  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
GHz  
ps  
Output Frequency  
3
tPD  
Propagation Delay; NOTE 1  
Output Skew; NOTE 4, 6  
Bank Skew; NOTE 3, 4  
500  
15  
tsk(o)  
tsk(b)  
ps  
15  
ps  
Buffer Additive Phase Jitter, RMS; Refer  
to Additive Phase Jitter Section  
100MHz, Integration Range:  
12kHz – 20MHz  
tjit  
0.15  
ps  
tR / tF  
odc  
Output Rise/Fall Time  
Output Duty Cycle  
20% to 80%  
100  
49  
200  
51  
ps  
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is  
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium  
has been reached under these conditions.  
NOTE: All parameters are measured at 550MHz, unless otherwise noted.  
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.  
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross  
points.  
NOTE 3: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.  
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.  
Table 5B. LVDS AC Characteristics, VDD = VTAP = 2.5V 5%, TA = -40°C to 85°C  
Symbol  
fMAX  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
GHz  
ps  
Output Frequency  
3
tPD  
Propagation Delay; NOTE 1  
Output Skew; NOTE 4, 6  
Bank Skew; NOTE 3, 4  
500  
15  
tsk(o)  
tsk(b)  
ps  
15  
ps  
Buffer Additive Phase Jitter, RMS; Refer  
to Additive Phase Jitter Section  
100MHz, Integration Range:  
12kHz – 20MHz  
tjit  
0.13  
ps  
tR / tF  
odc  
Output Rise/Fall Time  
Output Duty Cycle  
20% to 80%  
100  
49  
200  
51  
ps  
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is  
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium  
has been reached under these conditions.  
NOTE: All parameters are measured at 550MHz, unless otherwise noted.  
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.  
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross  
points.  
NOTE 3: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.  
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.  
ICS854S204BGI REVISION B NOVEMBER 18, 2011  
6
©2011 Integrated Device Technology, Inc.  
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