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854S013BGLF PDF预览

854S013BGLF

更新时间: 2024-02-16 06:07:01
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
14页 664K
描述
Clock Driver, S Series, 3 True Output(s), 3 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-20

854S013BGLF 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:6.50 X 4.40 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-20
针数:20Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.84系列:S
输入调节:STANDARDJESD-30 代码:R-PDSO-G20
JESD-609代码:e3长度:6.5 mm
逻辑集成电路类型:CLOCK DRIVER湿度敏感等级:1
功能数量:2反相输出次数:3
端子数量:20实输出次数:3
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
Base Number Matches:1

854S013BGLF 数据手册

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ICS854S013  
LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER  
PRELIMINARY  
LVPECL Clock Input Interface  
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other  
differential signals. Both signals must meet the VPP and VCMR input  
requirements. Figures 2A to 2F show interface examples for the  
HiPerClockS PCLK/nPCLK input driven by the most common  
driver types. The input interfaces suggested here are examples  
only. If the driver is from another vendor, use their termination  
recommendation. Please consult with the vendor of the driver  
component to confirm the driver termination requirements.  
3.3V  
3.3V  
3.3V  
3.3V  
Zo = 50  
3.3V  
R1  
50  
R2  
50  
Zo = 50Ω  
Zo = 50Ω  
PCLK  
R1  
100  
PCLK  
nPCLK  
Zo = 50Ω  
HiPerClockS  
nPCLK  
CML Built-In Pullup  
PCLK/nPCLK  
HiPerClockS  
PCLK/nPCLK  
CML  
Figure 2A. HiPerClockS PCLK/nPCLK Input  
Figure 2B. HiPerClockS PCLK/nPCLK Input  
Driven by a Built-In Pullup CML Driver  
Driven by an Open Collector CML Driver  
3.3V  
3.3V  
3.3V  
3.3V  
3.3V  
R3  
125  
R4  
125  
3.3V  
R3  
84  
R4  
84  
Zo = 50Ω  
Zo = 50Ω  
C1  
C2  
Zo = 50Ω  
Zo = 50Ω  
3.3V LVPECL  
PCLK  
PCLK  
nPCLK  
nPCLK  
HiPerClockS  
PCLK/nPCLK  
HiPerClockS  
Input  
LVPECL  
R5  
100 - 200  
R6  
100 - 200  
R1  
125  
R2  
125  
R1  
84  
R2  
84  
Figure 2C. HiPerClockS PCLK/nPCLK Input  
Driven by a 3.3V LVPECL Driver  
Figure 2D. HiPerClockS PCLK/nPCLK Input Driven by  
a 3.3V LVPECL Driver with AC Couple  
2.5V  
3.3V  
3.3V  
3.3V  
2.5V  
3.3V  
R3  
120  
R4  
120  
R3  
1k  
R4  
1k  
Zo = 50Ω  
Zo = 50Ω  
Zo = 60Ω  
Zo = 60Ω  
C1  
C2  
PCLK  
PCLK  
R5  
100  
nPCLK  
nPCLK  
HiPerClockS  
PCLK/nPCLK  
HiPerClockS  
PCLK/nPCLK  
LVDS  
SSTL  
R1  
1k  
R2  
1k  
R1  
120  
R2  
120  
Figure 2E. HiPerClockS PCLK/nPCLK Input  
Driven by an SSTL Driver  
Figure 2F. HiPerClockS PCLK/nPCLK Input  
Driven by a 3.3V LVDS Driver  
IDT™ / ICS™ LVDS FANOUT BUFFER  
9
ICS854S013BG REV. A FEBRUARY 26, 2008  

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