Datasheet > 853S111B_17

853S111B_17

更新时间： 2022-02-26 10:52:31

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
26页	601K
描述
Low Skew Different ial-to-2 .5V, 3.3V LVPECL/ECL

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853S111B_17 数据手册

853S111B Datasheet

Pin Descriptions and Characteristics

Table 1. Pin Descriptions

Number

Name

Type

Description

V_CC

Power

Input

Positive supply pin.

Clock select input. When HIGH, selects PCLK1/nPCLK1 inputs. When

LOW, selects PCLK0/nPCLK0 inputs. LVPECL interface levels. Also

accepts standard LVCMOS input levels.

CLK_SEL

Pulldown

PCLK0

Input

Non-inverting differential LVPECL clock input.

Pullup/

Pulldown

nPCLK0

Inverting differential LVPECL clock input. V_CC/2 default when left floating.

V_BB

Output

Input

Bias voltage to be connected for single-ended applications.

Non-inverting differential LVPECL clock input.

PCLK1

Pulldown

Pullup/

Pulldown

nPCLK1

Input

Inverting differential LVPECL clock input. V_CC/2 default when left floating.

V_EE

Power

Output

Negative supply pin.

9, 16, 25, 32

10, 11

V_CCO

Output supply pins.

Differential output pair. LVPECL/ECL interface levels.

nQ9, Q9

nQ8, Q8

nQ7, Q7

nQ6, Q6

nQ5, Q5

nQ4, Q4

nQ3, Q3

nQ2, Q2

nQ1, Q1

nQ0, Q0

12, 13

14, 15

17, 18

19, 20

21, 22

23, 24

26, 27

28, 29

30, 31

Output

Differential output pair. LVPECL/ECL interface levels.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

k

R_PULLDOWN

R_VCC/2

Input Pulldown Resistor

RPullup/Pulldown Resistors

k

November 9, 2017

123 4 5 6 7...26

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