Datasheet > 853S031BYILF

853S031BYILF

更新时间： 2022-02-26 14:10:18

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
22页	1005K
描述
LVPECL/ECL Fanout Buffer

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853S031BYILF 数据手册

ICS853S031I Data Sheet

LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

Function Tables

Table 3A. Control Input Function Table

Inputs

Outputs

CLK_EN

CLK_SEL

Selected Sources

CLK, nCLK

Q0:Q8

Disabled:LOW

Enabled

nQ0:nQ8

Disabled: HIGH

Enabled

PCLK, nPCLK

CLK, nCLK

PCLK, nPCLK

Enabled

After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.

In the active mode, the state of the outputs are a function of the CLK, nCLK and PCLK, nPCLK inputs as described in Table 3B.

Enabled

Disabled

nCLK, nPCLK

CLK, PCLK

CLK_EN

nQ[0:8]

Q[0:8]

Figure 1. CLK_EN Timing Diagram

Table 3B. Clock Input Function Table

Inputs

Outputs

Q0:Q8

CLK or PCLK

nCLK or nPCLK

nQ0:nQ8

HIGH

LOW

Input to Output Mode

Differential to Differential

Single-Ended to Differential

Polarity

Non-Inverting

Inverting

LOW

HIGH

LOW

HIGH

LOW

Biased; NOTE 1

HIGH

LOW

Biased; NOTE 1

LOW

HIGH

Inverting

Note 1: Please refer to the Applications Information, “Wiring the Differential Input to Accept Single Ended Levels”.

ICS853S031BYI REVISION A AUGUST 17, 2011

1 234 5 6 7...22

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