4:1, Differential-To-3.3V, 2.5V
LVPECL/ECL Clock Data Multiplexer
853S057
DATASHEET
Description
Features
The 853S057 is a 4:1 Differential-to-3.3V or 2.5V LVPECL/ECL
Clock/Data Multiplexer which can operate up to 3GHz. The 853S057
has 4 differential selectable clock input pairs. The CLK, nCLK input
pairs can accept LVPECL, LVDS, CML or SSTL levels. The fully
differential architecture and low propagation delay make it ideal for
use in clock distribution circuits. The multiplexer select control inputs
have ECL/LVPECL interface levels. The select pins have internal
pull-down resistors.
• High speed 4:1 differential multiplexer
• One differential 3.3V, 2.5V LVPECL/ECL output
• Four differential CLKx, nCLKx input pairs
• Differential CLKx, nCLKx pairs can accept the following interface
levels: LVPECL, LVDS, CML, SSTL
• Maximum input/output frequency: 3GHz
• Additive phase jitter, RMS at 622.08MHz: 0.073ps (typical)
• Part-to-part skew: 250ps (maximum)
• Propagation delay: 615ps (maximum)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.465V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.465V to -2.375V
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) packages
Block Diagram
Pin Assignment
VCC
CLK0
1
2
20
19
VCC
SEL1
Pulldown
CLK0
nCLK0
Pulldown
0 0
(default)
nCLK0
CLK1
3
4
18
17
SEL0
VCC
Q
nQ
VCC
Pulldown
Pulldown
CLK1
nCLK1
0 1
1 0
nCLK1
CLK2
nCLK2
5
6
7
16
15
14
13
12
11
Q
nQ
Pulldown
Pulldown
CLK2
nCLK2
VBB1
CLK3
8
nCLK3
VEE
9
10
VBB2
VEE
Pulldown
Pulldown
CLK3
1 1
nCLK3
853S057
Pulldown
Pulldown
SEL1
SEL0
VBB1
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
package body
VBB2
G Package
Top View
853S057AGI AUGUST 13, 2021
1
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