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853S024AYLF PDF预览

853S024AYLF

更新时间: 2024-01-01 06:29:09
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器逻辑集成电路
页数 文件大小 规格书
16页 720K
描述
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER

853S024AYLF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TQFP
包装说明:10 X 10 MM, 1 MM HEIGHT, ROHS COMPLIANT, MS-026ACD, TQFP-64针数:64
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.8
Is Samacsys:N其他特性:ALSO OPERATES ON 2.5V SUPPLY
系列:853S输入调节:DIFFERENTIAL
JESD-30 代码:S-PQFP-G64JESD-609代码:e3
长度:10 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:64
实输出次数:24最高工作温度:70 °C
最低工作温度:输出特性:OPEN-EMITTER
封装主体材料:PLASTIC/EPOXY封装代码:HTFQFP
封装等效代码:TQFP64,.47SQ封装形状:SQUARE
封装形式:FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH峰值回流温度(摄氏度):260
电源:2.5/3.3 VProp。Delay @ Nom-Sup:0.8 ns
传播延迟(tpd):0.8 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.125 ns座面最大高度:1.2 mm
子类别:Clock Drivers最大供电电压 (Vsup):2.625 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10 mm
最小 fmax:2000 MHzBase Number Matches:1

853S024AYLF 数据手册

 浏览型号853S024AYLF的Datasheet PDF文件第5页浏览型号853S024AYLF的Datasheet PDF文件第6页浏览型号853S024AYLF的Datasheet PDF文件第7页浏览型号853S024AYLF的Datasheet PDF文件第9页浏览型号853S024AYLF的Datasheet PDF文件第10页浏览型号853S024AYLF的Datasheet PDF文件第11页 
ICS853S024  
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER  
PRELIMINARY  
Recommendations for Unused Input and Output Pins  
Inputs:  
Outputs:  
CLK/nCLK Inputs  
LVPECL Outputs  
For applications not requiring the use of the differential input, both  
CLK and nCLK can be left floating. Though not required, but for  
additional protection, a 1kresistor can be tied from CLK to  
ground.  
All unused LVPECL outputs can be left floating. We recommend  
that there is no trace attached. Both sides of the differential output  
pair should either be left floating or terminated.  
Termination for 3.3V LVPECL Outputs  
The clock layout topology shown below is a typical termination for  
LVPECL outputs. The two different layouts mentioned are  
recommended only as guidelines.  
transmission lines. Matched impedance techniques should be  
used to maximize operating frequency and minimize signal  
distortion. Figures 3A and 3B show two different layouts which are  
recommended only as guidelines. Other suitable clock layouts may  
exist and it would be recommended that the board designers  
simulate to guarantee compatibility across all printed circuit and  
clock component process variations.  
FOUT and nFOUT are low impedance follower outputs that  
generate ECL/LVPECL compatible outputs. Therefore, terminating  
resistors (DC current path to ground) or current sources must be  
used for functionality. These outputs are designed to drive 50Ω  
3.3V  
Zo = 50  
125Ω  
125Ω  
FOUT  
FIN  
Z
Z
o = 50Ω  
o = 50Ω  
Zo = 50Ω  
FOUT  
FIN  
50Ω  
50Ω  
VCC - 2V  
1
RTT =  
Zo  
RTT  
((VOH + VOL) / (VCC – 2)) – 2  
84Ω  
84Ω  
Figure 3A. 3.3V LVPECL Output Termination  
Figure 3B. 3.3V LVPECL Output Termination  
LOW SKEW LVPECL FANOUT BUFFER  
8
ICS853S024AY REV. A APRIL 30, 2008  

853S024AYLF 替代型号

型号 品牌 替代类型 描述 数据表
8344AYI-01LF IDT

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Low Skew, 1-to-24 Differential-to-LVCMOS/LVTTL Fanout Buffer
8344AY-01LF IDT

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LOW SKEW, 1-TO-24 DIFFERENTIALTO-LVCMOS/LVTTL FANOUT BUFFER

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