ICS853S031I
Low Skew, 1-to-9, Differential-to-3.3V,
2.5V LVPECL/ECL Fanout Buffer
DATA SHEET
General Description
Features
The ICS853S031I is a low skew, high performance 1-to-9
Differential-to-2.5V/3.3V LVPECL/ECL Fanout Buffer. The
ICS853S031I has two selectable clock inputs. The CLK, nCLK pair
can accept most standard differential input levels. The PCLK, nPCLK
pair can accept LVPECL, LVDS, CML or SSTL input levels. The clock
enable is internally synchronized to eliminate runt pulses on the
outputs during asynchronous assertion/deassertion of the clock
enable pin.
ꢀ Nine differential 2.5V, 3.3V LVPECL/ECL outputs
ꢀ Selectable differential CLK, nCLK or LVPECL clock inputs
ꢀ CLK, nCLK pair can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, HCSL, SSTL
ꢀ PCLK, nPCLK supports the following input types: LVPECL, LVDS,
CML, SSTL
ꢀ Output frequency: 1.6GHz (maximum)
ꢀ Translates any single-ended input signal (LVCMOS, LVTTL, GTL)
to 3.3V LVPECL levels with resistor bias on nCLK or nPCLK
inputs
Guaranteed output and part-to-part skew characteristics make the
ICS853S031I ideal for high performance workstation and server
applications.
ꢀ Output skew: 20ps (typical)
ꢀ Part-to-part skew: 90ps (typical)
ꢀ Propagation delay: 885ps (typical), PCLK
ꢀ LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.465V, VEE = 0V
ꢀ ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.465V to -2.375V
ꢀ -40°C to 85°C ambient operating temperature
ꢀ Available lead-free (RoHS 6) package
Block Diagram
Pullup
CLK_EN
D
Q
Pin Assignment
LE
Pulldown
CLK
0
1
Pullup
Q0
nCLK
nQ0
Pulldown
Pullup
PCLK
32 31 30 29 28 27 26 25
nPCLK
Q1
1
2
3
4
5
6
7
8
VCC
VCCO
24
23
22
21
20
nQ1
Pulldown
CLK_SEL
CLK
Q3
Q2
nCLK
nQ3
Q4
nQ2
CLK_SEL
PCLK
Q3
nQ4
nQ3
nPCLK
VEE
Q5
19
18
17
Q4
nQ5
VCCO
nQ4
Q5
CLK_EN
9
10 11 12 13 14 15 16
nQ5
Q6
ICS853S031I
nQ6
32-Lead LQFP
Q7
7mm x 7mm x 1.4mm package body
Y Package
Top View
nQ7
Q8
nQ8
ICS853S031BYI REVISION A AUGUST 17, 2011
1
©2011 Integrated Device Technology, Inc.