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85357AG-01 PDF预览

85357AG-01

更新时间: 2024-11-07 14:47:43
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管逻辑集成电路
页数 文件大小 规格书
14页 165K
描述
Multiplexer, 85357 Series, 1-Func, 4 Line Input, 1 Line Output, Complementary Output, PDSO20, 4.40 X 6.50 MM, 0.90 MM HEIGHT, MO-153, TSSOP-20

85357AG-01 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:4.40 X 6.50 MM, 0.90 MM HEIGHT, MO-153, TSSOP-20针数:20
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.67
Is Samacsys:N其他特性:ECL MODE: VCC = 0V WITH VEE = -3.135V TO -3.465V
系列:85357JESD-30 代码:R-PDSO-G20
JESD-609代码:e0长度:6.5 mm
逻辑集成电路类型:MULTIPLEXER湿度敏感等级:1
功能数量:1输入次数:4
输出次数:1端子数量:20
最高工作温度:70 °C最低工作温度:
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):225电源:3.3 V
Prop。Delay @ Nom-Sup:1.5 ns传播延迟(tpd):1.5 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
Base Number Matches:1

85357AG-01 数据手册

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ICS85357-01  
4:1 OR 2:1  
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER  
GENERAL DESCRIPTION  
FEATURES  
The ICS85357-01 is a 4:1 or 2:1 Differential-to-3.3V High speed differential multiplexer. The device can be  
LVPECL / ECL clock multiplexer which can operate up to  
750MHz. The ICS85357-01 has 4 selectable clock inputs.  
The CLK, nCLK pair can accept most standard differential  
input levels. The device can operateusing a 3.3V LVPECL  
(VEE = 0V, VCC = 3.135V to 3.465V) or 3.3V ECL (VCC = 0V, VEE  
= -3.135V to -3.465V). The fully differential architecture and  
low propagation delay make itideal for use in clock  
distribution circuits. The select pins have internal pulldown  
resistors. Leaving one input unconnected (pulled to logic  
low by the internal resistor) will transformthe device into a  
2:1 multiplexer. The SEL1 pin is the most significant bit and  
the binary number applied to the select pins will select the  
same numbered data input (i.e., 00selects CLK0, nCLK0).  
configured as either a 4:1 or 2:1 multiplexer  
One differential 3.3V LVPECL output  
Four selectable CLK, nCLK inputs  
CLK, nCLK pair can accept the following differential  
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL  
Maximum output frequency: 750MHz  
Translates any single ended input signal to 3.3V  
LVPECL levels with resistor bias on nCLKx input  
Part-to-part skew: 150ps (maximum)  
Propagation delay: 1.5ns (maximum)  
LVPECL mode operating voltage supply range:  
VCC = 3.135V to 3.465V, VEE = 0V  
ECL mode operating voltage supply range:  
VCC = 0V, VEE = -3.135V to -3.465V  
0°C to 70°C ambient operating temperature  
Lead-Free package fully RoHS compliant  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
VCC  
CLK0  
nCLK0  
CLK1  
nCLK1  
CLK2  
nCLK2  
CLK3  
nCLK3  
VEE  
1
2
3
4
5
6
7
8
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
VCC  
SEL1  
SEL0  
VCC  
Q0  
nQ0  
VCC  
nc  
CLK0  
00  
nCLK0  
CLK1  
01  
nCLK1  
Q0  
nQ0  
CLK2  
10  
nCLK2  
9
10  
nc  
VEE  
CLK3  
11  
nCLK3  
ICS85357-01  
20-LeadTSSOP  
4.40mm x 6.50mm x 0.90mm body package  
G Package  
SEL0  
SEL1  
TopView  
85357AG-01  
www.idt.com  
REV. B JULY 29, 2010  
1

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