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8521BYI PDF预览

8521BYI

更新时间: 2024-11-09 15:26:55
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
14页 155K
描述
Clock Driver

8521BYI 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:,Reach Compliance Code:not_compliant
风险等级:5.92JESD-609代码:e0
湿度敏感等级:3端子面层:Tin/Lead (Sn85Pb15)
Base Number Matches:1

8521BYI 数据手册

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PRELIMINARY  
ICS8521I  
Integrated  
Circuit  
Systems, Inc.  
LOW SKEW, 1-TO-9  
DIFFERENTIAL-TO-HSTL FANOUT BUFFER  
GENERAL DESCRIPTION  
FEATURES  
The ICS8521I is a low skew, 1-to-9 Differential- Nine HSTL outputs  
ICS  
HiPerClockS™  
to-HSTL Fanout Buffer and a member of the  
Selectable differential CLK, nCLK or LVPECL clock inputs  
CLK, nCLK pair can accept the following differential  
input levels: LVPECL, LVDS, HSTL, SSTL, HCSL  
HiPerClockS™family of High Perfor mance Clock  
Solutions from ICS. The ICS8521I has two se-  
lectable clock inputs. The CLK, nCLK pair can  
accept most standard differential input levels. The PCLK,  
nPCLK pair can accept LVPECL, CML, or SSTL input levels.  
The clock enable is internally synchronized to eliminate runt  
pulses on the outputs during asynchronous assertion/  
deassertion of the clock enable pin.  
PCLK, nPCLK supports the following input types:  
LVPECL, CML, SSTL  
Maximum output frequency: 500MHz  
Output skew: 25ps (typical)  
Guaranteed output skew, part-to-part skew and crossover  
voltage characteristics make the ICS8521I ideal for today’s  
most advanced applications, such as IA64 and static RAMs.  
Part-to-part skew: 200ps (typical)  
Propagation delay: 1.3ns (typical)  
VOH = 1.4V (maximum)  
3.3V core, 1.8V output operating supply voltages  
-40°C to 85°C ambient operating temperature  
Available in both standard and lead-free RoHS  
compliant packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
D
CLK_EN  
Q
LE  
32 31 30 29 28 27 26 25  
CLK  
nCLK  
0
1
Q0  
1
2
3
4
5
6
7
8
VDD  
CLK  
24  
VDDO  
PCLK  
nPCLK  
nQ0  
23 Q3  
22 nQ3  
21 Q4  
20 nQ4  
19 Q5  
18 nQ5  
Q1  
nQ1  
nCLK  
CLK_SEL  
PCLK  
CLK_SEL  
ICS8521I  
9 10 11 12 13 14 15 16  
32-Lead LQFP  
Q2  
nQ2  
nPCLK  
GND  
Q3  
nQ3  
CLK_EN  
17  
VDDO  
Q4  
nQ4  
Q5  
nQ5  
Q6  
nQ6  
7mm x 7mm x 1.4mm package body  
Y Package  
TopView  
Q7  
nQ7  
Q8  
nQ8  
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial  
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.  
8521BYI  
www.icst.com/products/hiperclocks.html  
REV.A NOVEMBER 17, 2005  
1

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