Datasheet > 85102AGILF

85102AGILF

更新时间： 2024-01-30 21:55:58

品牌	Logo	应用领域
艾迪悌 - IDT		驱动光电二极管逻辑集成电路
页数	文件大小	规格书
17页	244K
描述
Low Skew, 1-to-2, Differential/LVCMOS HCSL Fanout Buffer

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技术参数
数据手册
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85102AGILF 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	TSSOP
包装说明：	TSSOP, TSSOP16,.25	针数：	16
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	1.03
系列：	85102	输入调节：	DIFFERENTIAL MUX
JESD-30 代码：	R-PDSO-G16	JESD-609代码：	e3
长度：	5 mm	逻辑集成电路类型：	LOW SKEW CLOCK DRIVER
湿度敏感等级：	1	功能数量：	1
反相输出次数：		端子数量：	16
实输出次数：	2	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装等效代码：	TSSOP16,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	电源：	3.3 V
Prop。Delay @ Nom-Sup：	3.2 ns	认证状态：	Not Qualified
座面最大高度：	1.2 mm	子类别：	Clock Drivers
最大供电电压 (Vsup)：	3.63 V	最小供电电压 (Vsup)：	2.97 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn) - annealed
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	4.4 mm	Base Number Matches：	1

85102AGILF 数据手册

85102 DATA SHEET

APPLICATIONS INFORMATION

RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS

INPUTS:

OUTPUTS:

CLK INPUT

DIFFERENTIAL OUTPUTs

For applications not requiring the use of a clock input, it can be left

ﬂoating. Though not required, but for additional protection, a 1kΩ

resistor can be tied from the CLK input to ground.

All unused differential outputs can be left ﬂoating. We recommend

that there is no trace attached. Both sides of the differential output

pair should either be left ﬂoating or terminated.

CLK/nCLK I^NPUTS

For applications not requiring the use of the differential input, both

CLK and nCLK can be left ﬂoating. Though not required, but for

additional protection, a 1kΩ resistor can be tied from CLK to ground.

LVCMOS C^ONTROLPINS

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional protection.

A 1kΩ resistor can be used.

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

Figure 2 shows how a differential input can be wired to accept single

ended levels. The reference voltage V_REF= V_DD/2 is generated by

the bias resistors R1 and R2.The bypass capacitor (C1) is used to

help ﬁlter noise on the DC bias. This bias circuit should be located

as close to the input pin as possible. The ratio of R1 and R2 might

need to be adjusted to position the V_REFin the center of the input

voltage swing. For example, if the input clock swing is 2.5V and V_DD

= 3.3V, R1 and R2 value should be adjusted to set V_REFat 1.25V.

The values below are for when both the single-ended swing andV_DD

are at the same voltage.This conﬁguration requires that the sum of

the output impedance of the driver (Ro) and the series resistance

(Rs) equals the transmission line impedance. In addition, matched

termination at the input will attenuate the signal in half.This can be

done in one of two ways.First, R3 and R4 in parallel should equal the

transmission line impedance. For most 50 applications, R3 and R4

can be 100Ω.The values of the resistors can be increased to reduce

the loading for slower and weaker LVCMOS driver. When using

single ended signaling, the noise rejection beneﬁts of differential

signaling are reduced.Even though the differential input can handle

full rail LVCMOS signaling, it is recommended that the amplitude

be reduced. The datasheet speciﬁes a lower differential amplitude,

however this only applies to differential signals. For single-ended

applications, the swing can be larger, however V cannot be less

than -0.3V and V_IHcannot be more than V_DD+ 0.3V.^ILThough some of

the recommended components might not be used, the pads should

be placed in the layout.They can be utilized for debugging purposes.

The datasheet speciﬁcations are characterized and guaranteed by

using a differential signal.

FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

REVISION B 12/19/14

Low Skew, 1-to-2, Differential/LVCMOS-to-0.7V HCSL

Fanout Buffer

1...6 7 8910 11 12...17

中文翻译

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85102AGILF 替代型号

型号	品牌	替代类型	描述	数据表
ICS85102AGILF	IDT	功能相似	Low Skew Clock Driver, 85102 Series, 2 True Output(s), 0 Inverted Output(s), PDSO16, 4.40
ICS85102AGILFT	IDT	功能相似	Low Skew Clock Driver, 85102 Series, 2 True Output(s), 0 Inverted Output(s), PDSO16, 4.40

与85102AGILF相关器件

型号	品牌	描述	获取价格	数据表
85102AGILFT	IDT	Low Skew, 1-to-2, Differential/LVCMOS HCSL Fanout Buffer	获取价格
85102AGIT	IDT	Low Skew Clock Driver, 85102 Series, 2 True Output(s), 0 Inverted Output(s), PDSO16, 4.40	获取价格
85102E	AMPHENOL	MIL SERIES CONNECTOR	获取价格
851-02E106P50	ETC	SQUARE FLANGE RECEPT. 6 WAYS	获取价格
851-02E1210P50	ETC	SQUARE FLANGE RECEPT. 8 WAYS	获取价格
851-02E123P50	ETC	SQUARE FLANGE RECEPT. 3 WAYS	获取价格

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85102AGILF

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