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84C24 PDF预览

84C24

更新时间: 2024-11-06 23:25:39
品牌 Logo 应用领域
其他 - ETC 以太网
页数 文件大小 规格书
51页 435K
描述
84C24 Quad 10BASE-T Ethernet Media Interface Adapter manual 6/96

84C24 数据手册

 浏览型号84C24的Datasheet PDF文件第2页浏览型号84C24的Datasheet PDF文件第3页浏览型号84C24的Datasheet PDF文件第4页浏览型号84C24的Datasheet PDF文件第5页浏览型号84C24的Datasheet PDF文件第6页浏览型号84C24的Datasheet PDF文件第7页 
Full Duplex  
84C24  
Quad 10Base-T Ethernet  
Media Interface Adapter  
96200  
Features  
Note: Check for latest Data Sheet revision  
before starting any designs.  
Single Chip Interface Between Ethernet Controller  
And Twisted Pair Wire  
SEEQ Data Sheets are now on the Web, at  
www.lsilogic.com.  
Four Independent Channels In One IC  
On Chip Wave Shaping And Filters - No External  
Filters Required  
This document is an LSI Logic document. Any  
reference to SEEQ Technology should be  
considered LSI Logic.  
Few External Components  
Meets All Applicable IEEE 802.3 and 10Base-T  
Standards  
- Transmit Disable  
- Programmable LED Output  
Direct Interface To SEEQ, Intel, AMD, NSC  
Controllers  
Full/Half Duplex AutoNegotiation Per  
- Loopback  
Status Outputs  
- Link  
IEEE 802.3 Clause 28  
Many User Features And Options  
- Half/Full Duplex AutoNegotiation  
- Universal Controller Interface  
- Autopolarity  
- Polarity  
- Jabber  
- Full Duplex  
- AutoNegotiation  
- Smart Squelch  
- Interrupt  
LED Outputs  
- Link  
- Transmit Level Adjust  
- Receive Level Adjust  
- 100/150 Ohm Cable  
- Powerdown  
- Full Duplex  
- User Programmable  
- SQE Disable  
- Link Disable  
- Jabber Disable  
Serial Port For Configuration And Status  
68L PLCC  
Pin Configuration  
9
2
68  
1 67  
8
7
6
5
4
3
10  
11  
SCLK  
SDIO  
GND5  
CS  
12  
13  
14  
INT  
PLED3  
PLED2  
PLED1  
15  
16  
17  
18  
19  
20  
21  
22  
23  
84C24  
68 Pin PLCC  
Top View  
V
CC3  
PLED0  
RESET  
GND3  
OSCIN  
V
CC2  
24  
GND2  
26  
44  
27  
1
MD400147/A  

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