Datasheet > 843002CY-31LFT

843002CY-31LFT

更新时间： 2024-11-02 18:47:11

品牌	Logo	应用领域
艾迪悌 - IDT		时钟外围集成电路晶体
页数	文件大小	规格书
28页	773K
描述
Clock Generator, 700MHz, PQFP64, 10 X 10 MM, 1 MM HEIGHT, ROHS COMPLIANT, MS-026, TQFP-64

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843002CY-31LFT 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFP
包装说明：	TFQFP,	针数：	64
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.22
JESD-30 代码：	S-PQFP-G64	JESD-609代码：	e3
长度：	10 mm	端子数量：	64
最高工作温度：	70 °C	最低工作温度：
最大输出时钟频率：	700 MHz	封装主体材料：	PLASTIC/EPOXY
封装代码：	TFQFP	封装形状：	SQUARE
封装形式：	FLATPACK, THIN PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	260
主时钟/晶体标称频率：	25 MHz	认证状态：	Not Qualified
座面最大高度：	1.2 mm	最大供电电压：	3.465 V
最小供电电压：	3.135 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	MATTE TIN
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	10 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER
Base Number Matches：	1

843002CY-31LFT 数据手册

PRELIMINARY

FEMTOCLOCKS™ VCXO BASED

FREQUENCY TRANSLATOR/JITTER ATTENUATOR

ICS843002-31

GENERAL DESCRIPTION

FEATURES

The ICS843002-31 is

a member of the

• Outputs:

ICS

HiPerClockS™

HiperClockS™ family of high performance clock

solutions from IDT. This monolithic device is a high-

performance, PLL-based synchronous clock

generator and jitter attenuation circuit. The

• Two high frequency differential LVPECL outputs

Output frequency: up to 700MHz

• One LVCMOS/LVTTL VCXO PLL output with output enable

• One Reference clock output with output enable

• One LOCK detect output

ICS843002-31 contains two clock multiplication stages that are

cascaded in series. The first stage is a VCXO-based PLL that

is optimized to provide reference clock jitter attenuation, to be

jitter tolerant, and to provide a stable reference clock for the

second multiplication stage.The second stage is the proprietary

IDT FemtoClock™circuit which is a high-frequency, sub-

picosecond clock multiplier.

• Input mux supports 3 selectable inputs: one differential input

pair and two LVCMOS/LVTTL input clocks

• 13-bit VCXO PLL feedback and reference dividers provide

wide range of frequency translation ratio options

• FemtoClock frequency multiplier supports rate of:

The VCXO PLL has an on-chip VCXO circuit that uses an

external, inexpensive pullable crystal in the 17.5 to 25MHz

range. The PLL includes 13 bit reference and feedback

dividers supporting complex PLL multiplication ratios and

input reference clock rates as low as 2.3kHz. External loop

filter components are used (two resistors and two capacitors)

to achieve the low loop bandwidth needed for jitter atten-

uation of a recovered data clock.

560MHz - 700MHz

• ‘Lock Detect’ output reports lock status of VCXO PLL

• VCXO PLL circuit provides jitter attenuation with

loop bandwidth of 250Hz and below (user adjustable)

• RMS phase jitter, random at 12kHz to 20MHz:

<1ps (design target)

The FemtoClock circuit can multiply the VCXO crystal frequency

by a factor of 28 or 32 (selectable) and provide a clock output of

up to 700MHz.

• 3.3V supply voltage

• 0°C to 70°C ambient operating temperature

• Industrial temperature information available upon request

Clock Input/Output Configuration:

• Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages

• Clock Inputs - one differential pair, two singled ended

(mux selected)

• Differential input pair can support LVPECL, LVDS,

LVHSTL, SSTL, HCSL or single-ended LVCMOS

or LVTTL levels

PIN ASSIGNMENT

• Singled ended inputs can support LVCMOS or

LVTTL levels

64 63 62 61 60 59 58 57 56 55 54 53 52 5150 49

• Clock Outputs, FemtoClockS two LVPECL pairs

(selectable output dividers)

VEE

LF1

LF0

REF_CLK

VCLK

LOCK

V^CCO_CMOS

nQB

• Clock Output, VCXO – one single ended output

(at VCXO crystal frequency)

ISET

V^EE

NV1

• Clock Output, other – VCXO reference clock

NV0

ICS843002-31

64-Lead TQFP, EPAD

10mm x 10mm x 1.0mm

package body

V^CC

V^EE

Example Applications:

nQA

CLK0

nCLK0

OE_REF

CLK1

V^CC

• SONET/SDH line card clock generator (up to 622.08MHz

for OC-48) using 8kHz frame clock as input reference

Y package

Top View

V^CCO_PECL

• Jitter attenuation of a recovered communications clock

NPB0

NPB1

NPB2

V^CCA

• Complex-ratio clock frequency translation between

various communication protocols, such as:

• For telecom, OC-12 to E3 rate conversion, 622.08MHz

to 34.368MHz, PLL ratio of 179/32

SEL1

SEL0

CLK2

1718 19 20 2122 23 2425 26 27 28 29 30 31 32

• For digital video, ITU-R601 to SMPTE 252M/59.94,

27MHz to 74.17582MHz, PLL ratio of 250/91

The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization

and/or qualification.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.

IDT^™/ ICS^™VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR

ICS843002CY-31 REV. B NOVEMBER 8, 2006

12 3 4 5 6 7...28

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