Datasheet > 843002BKI-72LF

843002BKI-72LF

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
艾迪悌 - IDT		时钟发生器石英晶振压控振荡器衰减器
页数	文件大小	规格书
18页	296K
描述
FEMTOCLOCKS⑩ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR

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843002BKI-72LF 数据手册

ICS843002I-72

FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR

TABLE 1. PIN DESCRIPTIONS

Number

Name

Type

Analog

Input/Output

Description

1, 2

LF1, LF0

Loop filter connection node pins.

Analog

Input/Output

ISET

V_CC

Charge pump current setting pin.

Core power supply pins.

4, 5, 22, 28,

29, 30

Power

6, 7, 9, 10, 13,

17, 23, 26, 27

V_EE

Power

Input

Negative supply pins.

CLK

nOE

Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.

Output enable pin. When LOW, output is enabled.

Pulldown

LVCMOS/LVTTL interface levels. See Table 3.

14, 20, 21

15, 16

18, 19

V_CCA

V_CCO

Power

Analog supply pin.

Output power supply pin.

Q0, nQ0

Q1, nQ1

LOCK_DT

Output

Unused

Differential clock output pair. LVPECL interface levels.

Lock detect. Logic HIGH when VCXO PLL loop is locked.

No connect.

31,

XTAL_OUT,

XTAL_IN

Crystal oscillator interface. XTAL_OUT is the output.

XTAL_IN is the input.

Input

NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.

TABLE 2. PIN CHARACTERISTICS

Symbol Parameter

Test Conditions

Minimum Typical Maximum Units

C_IN

Input Capacitance

R_PULLDOWNInput Pulldown Resistor

kΩ

TABLE 3. INPUT REFERENCE SELECTION FUNCTION TABLE

Inputs

Outputs

Q0/nQ0, Q1/nQ1

Enabled

nOE

Hi-Z

IDT^™/ ICS^™WCDMA CLOCK GENERATOR/JITTER ATTENUATOR

ICS843002BKI-72 REV. A NOVEMBER 21, 2007

1 234 5 6 7...18

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