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841608AKIT PDF预览

841608AKIT

更新时间: 2024-11-04 12:52:47
品牌 Logo 应用领域
艾迪悌 - IDT 晶体时钟发生器微控制器和处理器外围集成电路
页数 文件大小 规格书
17页 397K
描述
FEMTOCLOCKS CRYSTAL-TO-HCSL CLOCK GENERATOR VCO: 500MHz

841608AKIT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFN
包装说明:5 X 5 MM, 0.95 MM HEIGHT, MO-220, VFQFN-32针数:32
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.38
JESD-30 代码:S-XQCC-N32JESD-609代码:e0
长度:5 mm湿度敏感等级:3
端子数量:32最高工作温度:85 °C
最低工作温度:-40 °C最大输出时钟频率:125 MHz
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC32,.2SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):225
电源:3.3 V主时钟/晶体标称频率:25 MHz
认证状态:Not Qualified座面最大高度:1 mm
子类别:Clock Generators最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:5 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

841608AKIT 数据手册

 浏览型号841608AKIT的Datasheet PDF文件第2页浏览型号841608AKIT的Datasheet PDF文件第3页浏览型号841608AKIT的Datasheet PDF文件第4页浏览型号841608AKIT的Datasheet PDF文件第5页浏览型号841608AKIT的Datasheet PDF文件第6页浏览型号841608AKIT的Datasheet PDF文件第7页 
FEMTOCLOCKS™ CRYSTAL-TO-HCSL  
CLOCK GENERATOR  
ICS841608I  
GENERAL DESCRIPTION  
FEATURES  
• Eight HCSL outputs: configurable for PCIe (100MHz)  
and sRIO (125MHz) clock signals  
The ICS841608I is an optimized PCIe and sRIO  
ICS  
HiPerClockS™  
clock generator and member of the HiPerClocks™  
family of high-performance clock solutions from IDT.  
• Selectable crystal oscillator interface, 25MHz,  
18pF parallel resonant crystal or LVCMOS/LVTTL  
single-ended reference clock input  
The device uses a 25MHz parallel crystal to  
generate 100MHz and 125MHz clock signals,  
replacing solutions requiring multiple oscillator and fanout buffer  
solutions. The device has excellent phase jitter (<1ps rms)  
suitable for clock components requiring precise and low-jitter  
PCIe or sRIO or both clock signals. Designed for telecom,  
networking and industrial applications, the ICS841608I can also  
drive the high-speed sRIO and PCIe SerDes clock inputs of  
communication processors, DSPs, switches and bridges.  
• Supports the following output frequencies:  
100MHz or 125MHz  
• VCO: 500MHz  
• PLL bypass and output enable  
• PCI Express (2.5Gb/s) and Gen 2 (5 Gb/s) jitter compliant  
• RMS phase jitter @125MHz, using a 25MHz crystal  
(1.875MHz – 20MHz): 0.37ps (typical)  
• Full 3.3V power supply mode  
• -40°C to 85°C ambient operating temperature  
• Available in both standard and (RoHs 5) lead-free (RoHS 6)  
packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
XTAL_IN  
Q0  
1
0
OSC  
nQ0  
FemtoClock  
PLL  
XTAL_OUT  
÷N  
0
32 31 30 29 28 27 26 25  
VCO = 500MHz  
÷4  
÷5 (default)  
Q1  
Pulldown  
REF_IN  
1
24  
1
2
3
4
5
6
7
8
XTAL_IN  
XTAL_OUT  
MR/nOE  
VDD  
VDD  
nQ7  
Q7  
nQ1  
23  
22  
21  
20  
19  
18  
Pulldown  
REF_SEL  
Q2  
nQ6  
Q6  
M = ÷20  
nQ2  
Q0  
IREF  
nQ0  
GND  
nQ5  
Q5  
Q3  
Pulldown  
Pulldown  
Q1  
BYPASS  
FSEL  
nQ3  
nQ1  
17  
9
10 11 12 13 14 15 16  
Q4  
nQ4  
Q5  
ICS841608I  
32-Lead VFQFN  
nQ5  
5mm x 5mm x 0.925mm  
package body  
K Package  
Q6  
Top View  
nQ6  
Q7  
nQ7  
Pulldown  
MR/nOE  
IDT/ ICSHCSL CLOCK GENERATOR  
1
ICS841608AKI REV. A JUNE 18, 2008  

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